===================================================================
@@ -31,6 +31,8 @@
bool "GA-M57SLI-S4"
config BOARD_GIGABYTE_GA785GMT
bool "GA-MA785GMT-UD2H"
+config BOARD_GIGABYTE_MA785GM
+ bool "GA-MA785GM-US2H"
config BOARD_GIGABYTE_MA78GM
bool "GA-MA78GM-US2H"
@@ -41,6 +43,7 @@
source "src/mainboard/gigabyte/ga-6bxe/Kconfig"
source "src/mainboard/gigabyte/m57sli/Kconfig"
source "src/mainboard/gigabyte/ma785gmt/Kconfig"
+source "src/mainboard/gigabyte/ma785gm/Kconfig"
source "src/mainboard/gigabyte/ma78gm/Kconfig"
config MAINBOARD_VENDOR
===================================================================
@@ -1,10 +1,10 @@
-if BOARD_AMD_TILAPIA_FAM10
+if BOARD_GIGABYTE_MA785GM
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
select CPU_AMD_SOCKET_AM3
- select DIMM_DDR3
+ select DIMM_DDR2
select DIMM_REGISTERED
select NORTHBRIDGE_AMD_AMDFAM10
select SOUTHBRIDGE_AMD_RS780
@@ -29,7 +29,7 @@
config MAINBOARD_DIR
string
- default amd/tilapia_fam10
+ default gigabyte/ma785gm
config APIC_ID_OFFSET
hex
@@ -37,7 +37,7 @@
config MAINBOARD_PART_NUMBER
string
- default "Tilapia (Fam10)"
+ default "GA-MA785GM-US2H"
config MAX_CPUS
int
@@ -69,7 +69,7 @@
config AMD_UCODE_PATCH_FILE
string
- default "mc_patch_010000b6.h"
+ default "mc_patch_01000086.h"
config RAMTOP
hex
@@ -91,4 +91,4 @@
hex
default 0x200000
-endif # BOARD_AMD_TILAPIA_FAM10
+endif # BOARD_GIGABYTE_MA785GM
===================================================================
@@ -1,7 +1,7 @@
-# sample config for amd/tilapia_fam10
+# sample config for gigabyte/ma785gm
chip northbridge/amd/amdfam10/root_complex
device lapic_cluster 0 on
- chip cpu/amd/socket_AM3 #L1 and DDR3
+ chip cpu/amd/socket_AM3 #L1 and DDR2
device lapic 0 on end
end
end
@@ -9,17 +9,17 @@
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
chip southbridge/amd/rs780
- device pci 0.0 on end # HT 0x9600
+ device pci 0.0 on end # HT 0x9601
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
- device pci 3.0 on end # PCIE P2P bridge 0x960b
+ device pci 3.0 on end # PCIE P2P bridge 0x960b
device pci 4.0 on end # PCIE P2P bridge 0x9604
device pci 5.0 off end # PCIE P2P bridge 0x9605
device pci 6.0 off end # PCIE P2P bridge 0x9606
device pci 7.0 off end # PCIE P2P bridge 0x9607
device pci 8.0 off end # NB/SB Link P2P bridge
device pci 9.0 on end #
- device pci a.0 on end #
+ device pci a.0 on end # PCIE P2P bridge 0x9609
register "gppsb_configuration" = "1" # Configuration B
register "gpp_configuration" = "3" # Configuration D default
register "port_enable" = "0x6fc"
@@ -108,35 +108,7 @@
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
-# device pci 00.5 on end
end
end #pci_domain
#for node 32 to node 63
-# device pci_domain 0 on
-# chip northbridge/amd/amdfam10
-# device pci 00.0 on end# northbridge
-# device pci 00.0 on end
-# device pci 00.0 on end
-# device pci 00.0 on end
-# device pci 00.1 on end
-# device pci 00.2 on end
-# device pci 00.3 on end
-# device pci 00.4 on end
-# device pci 00.5 on end
-# end
-# end #pci_domain
-
-# chip drivers/generic/debug
-# device pnp 0.0 off end # chip name
-# device pnp 0.1 on end # pci_regs_all
-# device pnp 0.2 off end # mem
-# device pnp 0.3 off end # cpuid
-# device pnp 0.4 off end # smbus_regs_all
-# device pnp 0.5 off end # dual core msr
-# device pnp 0.6 off end # cache size
-# device pnp 0.7 off end # tsc
-# device pnp 0.8 off end # hard reset
-# device pnp 0.9 off end # mcp55
-# device pnp 0.a on end # GH ext table
-# end
end
===================================================================
@@ -99,6 +99,7 @@
sb700_lpc_init();
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
+ it8718f_disable_reboot();
uart_init();
#if CONFIG_USBDEBUG
===================================================================
@@ -22,8 +22,8 @@
"DSDT.AML", /* Output filename */
"DSDT", /* Signature */
0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "AMD ", /* OEMID */
- "TILAPIA ", /* TABLE ID */
+ "GIGA ", /* OEMID */
+ "MA785GM", /* TABLE ID */
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */
===================================================================
@@ -48,7 +48,7 @@
void set_pcie_dereset(void);
void set_pcie_reset(void);
-u8 is_dev3_present(void);
+int is_dev3_present(void);
void set_pcie_dereset()
{
@@ -101,39 +101,12 @@
pci_write_config16(sm_dev, 0x7e, word);
}
-#if 0 /* TODO: */
-/********************************************************
-* tilapia uses SB700 GPIO8 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void get_ide_dma66(void)
-{
- u8 byte;
- /*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 4); /* Set Gpio8 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
-
- ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
- byte = pci_read_config8(ide_dev, 0x56);
- byte &= ~(7 << 0);
- if ((1 << 4) & pci_read_config8(sm_dev, 0xAA))
- byte |= 2 << 0; /* mode 2 */
- else
- byte |= 5 << 0; /* mode 5 */
- pci_write_config8(ide_dev, 0x56, byte);
-}
-#endif
-
/*
* justify the dev3 is exist or not
*/
-u8 is_dev3_present(void)
+int is_dev3_present(void)
{
u16 word;
device_t sm_dev;
@@ -279,12 +252,12 @@
}
/*************************************************
-* enable the dedicated function in tilapia board.
+* enable the dedicated function in ma785gm board.
* This function called early than rs780_enable.
*************************************************/
-static void tilapia_enable(device_t dev)
+static void ma785gm_enable(device_t dev)
{
- printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev);
+ printk(BIOS_INFO, "Mainboard Gigabyte ma785gm Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
msr_t msr, msr2;
@@ -346,6 +319,6 @@
}
struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD TILAPIA Mainboard")
- .enable_dev = tilapia_enable,
+ CHIP_NAME("GIGABYTE MA785GMT Mainboard")
+ .enable_dev = ma785gm_enable,
};