From patchwork Tue Jan 4 15:27:39 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Test SeaBIOS AHCI support Date: Tue, 04 Jan 2011 15:27:39 -0000 From: Neo The User X-Patchwork-Id: 2487 Message-Id: <256385.89886.qm@web114109.mail.gq1.yahoo.com> To: coreboot@coreboot.org Hello! New patch :) Sorry about that, I have little to no experience with subversion. Also I found out that the rebooting loop wasn't caused by the AHCI SATA being off, but rather the console level for serial output was below 7 in the coreboot config file... I found it very strange. Anyway, the real result of having AHCI SATA off in SeaBIOS causes the payload to just hang, before it says to press F12. With it on, I can access GRUB but I get kernel panics in any Linux distro. NetBSD also fails. I attached a new patch, using svn copy and such from Tilapia, keeping almost everything the same in the diff. After creating the diff, I poked around a bit more, but I couldn't solve the kernel panics. This isn't really a big concern for me personally but I thought it would be cool to have a board with over 1,100 reviews on newegg that would be supported by Coreboot. Might spark some attention as well. -Alec --- On Tue, 1/4/11, Peter Stuge wrote: > From: Peter Stuge > Subject: Re: [coreboot] Test SeaBIOS AHCI support > To: coreboot@coreboot.org > Date: Tuesday, January 4, 2011, 11:45 AM > Hi Alec, > > Neo The User wrote: > > I have attached the somewhat working port as a patch > > (ma785gm-us2h.patch) > > Cool! > > > > I hope the patch format is correct! > > Well, I'd say no. It is impossible to review this patch > because it > duplicates (nearly) all code for another board. > > It would be very good if you could start with a patch that > is simply > a diff from the ma785gmt board. > > Finally, when copying files later, into the new ma785gm > directory, > please make sure to use svn to do copies, so that patches > become much > smaller, or at the very least that the history is kept. > > But please first start with a diff against an existing > board. If the > differences are small enough maybe the same code can handle > both boards. > > > //Peter > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > Index: src/mainboard/gigabyte/Kconfig =================================================================== --- src/mainboard/gigabyte/Kconfig (revision 6239) +++ src/mainboard/gigabyte/Kconfig (working copy) @@ -31,6 +31,8 @@ bool "GA-M57SLI-S4" config BOARD_GIGABYTE_GA785GMT bool "GA-MA785GMT-UD2H" +config BOARD_GIGABYTE_MA785GM + bool "GA-MA785GM-US2H" config BOARD_GIGABYTE_MA78GM bool "GA-MA78GM-US2H" @@ -41,6 +43,7 @@ source "src/mainboard/gigabyte/ga-6bxe/Kconfig" source "src/mainboard/gigabyte/m57sli/Kconfig" source "src/mainboard/gigabyte/ma785gmt/Kconfig" +source "src/mainboard/gigabyte/ma785gm/Kconfig" source "src/mainboard/gigabyte/ma78gm/Kconfig" config MAINBOARD_VENDOR Index: src/mainboard/gigabyte/ma785gm/Kconfig =================================================================== --- src/mainboard/gigabyte/ma785gm/Kconfig (revision 6239) +++ src/mainboard/gigabyte/ma785gm/Kconfig (working copy) @@ -1,10 +1,10 @@ -if BOARD_AMD_TILAPIA_FAM10 +if BOARD_GIGABYTE_MA785GM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_AMD_SOCKET_AM3 - select DIMM_DDR3 + select DIMM_DDR2 select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_RS780 @@ -29,7 +29,7 @@ config MAINBOARD_DIR string - default amd/tilapia_fam10 + default gigabyte/ma785gm config APIC_ID_OFFSET hex @@ -37,7 +37,7 @@ config MAINBOARD_PART_NUMBER string - default "Tilapia (Fam10)" + default "GA-MA785GM-US2H" config MAX_CPUS int @@ -69,7 +69,7 @@ config AMD_UCODE_PATCH_FILE string - default "mc_patch_010000b6.h" + default "mc_patch_01000086.h" config RAMTOP hex @@ -91,4 +91,4 @@ hex default 0x200000 -endif # BOARD_AMD_TILAPIA_FAM10 +endif # BOARD_GIGABYTE_MA785GM Index: src/mainboard/gigabyte/ma785gm/devicetree.cb =================================================================== --- src/mainboard/gigabyte/ma785gm/devicetree.cb (revision 6239) +++ src/mainboard/gigabyte/ma785gm/devicetree.cb (working copy) @@ -1,7 +1,7 @@ -# sample config for amd/tilapia_fam10 +# sample config for gigabyte/ma785gm chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR3 + chip cpu/amd/socket_AM3 #L1 and DDR2 device lapic 0 on end end end @@ -9,17 +9,17 @@ chip northbridge/amd/amdfam10 device pci 18.0 on # northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 + device pci 0.0 on end # HT 0x9601 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b + device pci 3.0 on end # PCIE P2P bridge 0x960b device pci 4.0 on end # PCIE P2P bridge 0x9604 device pci 5.0 off end # PCIE P2P bridge 0x9605 device pci 6.0 off end # PCIE P2P bridge 0x9606 device pci 7.0 off end # PCIE P2P bridge 0x9607 device pci 8.0 off end # NB/SB Link P2P bridge device pci 9.0 on end # - device pci a.0 on end # + device pci a.0 on end # PCIE P2P bridge 0x9609 register "gppsb_configuration" = "1" # Configuration B register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" @@ -108,35 +108,7 @@ device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end -# device pci 00.5 on end end end #pci_domain #for node 32 to node 63 -# device pci_domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #pci_domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # hard reset -# device pnp 0.9 off end # mcp55 -# device pnp 0.a on end # GH ext table -# end end Index: src/mainboard/gigabyte/ma785gm/romstage.c =================================================================== --- src/mainboard/gigabyte/ma785gm/romstage.c (revision 6239) +++ src/mainboard/gigabyte/ma785gm/romstage.c (working copy) @@ -99,6 +99,7 @@ sb700_lpc_init(); it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + it8718f_disable_reboot(); uart_init(); #if CONFIG_USBDEBUG Index: src/mainboard/gigabyte/ma785gm/dsdt.asl =================================================================== --- src/mainboard/gigabyte/ma785gm/dsdt.asl (revision 6239) +++ src/mainboard/gigabyte/ma785gm/dsdt.asl (working copy) @@ -22,8 +22,8 @@ "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "TILAPIA ", /* TABLE ID */ + "GIGA ", /* OEMID */ + "MA785GM", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ Index: src/mainboard/gigabyte/ma785gm/mainboard.c =================================================================== --- src/mainboard/gigabyte/ma785gm/mainboard.c (revision 6239) +++ src/mainboard/gigabyte/ma785gm/mainboard.c (working copy) @@ -48,7 +48,7 @@ void set_pcie_dereset(void); void set_pcie_reset(void); -u8 is_dev3_present(void); +int is_dev3_present(void); void set_pcie_dereset() { @@ -101,39 +101,12 @@ pci_write_config16(sm_dev, 0x7e, word); } -#if 0 /* TODO: */ -/******************************************************** -* tilapia uses SB700 GPIO8 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 4); /* Set Gpio8 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 4) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif - /* * justify the dev3 is exist or not */ -u8 is_dev3_present(void) +int is_dev3_present(void) { u16 word; device_t sm_dev; @@ -279,12 +252,12 @@ } /************************************************* -* enable the dedicated function in tilapia board. +* enable the dedicated function in ma785gm board. * This function called early than rs780_enable. *************************************************/ -static void tilapia_enable(device_t dev) +static void ma785gm_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard Gigabyte ma785gm Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; @@ -346,6 +319,6 @@ } struct chip_operations mainboard_ops = { - CHIP_NAME("AMD TILAPIA Mainboard") - .enable_dev = tilapia_enable, + CHIP_NAME("GIGABYTE MA785GMT Mainboard") + .enable_dev = ma785gm_enable, };