From patchwork Mon Sep 14 00:46:38 2009
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Subject: unstable AMD Fam10h boot
Date: Mon, 14 Sep 2009 00:46:38 -0000
From: Marc Jones <marcj303@gmail.com>
X-Patchwork-Id: 252
Message-Id: <534e5dc20909131746s27fdac9bube60b3fec2535d8@mail.gmail.com>
To: ron minnich <rminnich@gmail.com>
Cc: coreboot@coreboot.org

On Tue, Sep 8, 2009 at 11:02 AM, Marc Jones <marcj303@gmail.com> wrote:
> On Sun, Sep 6, 2009 at 4:32 PM, ron minnich<rminnich@gmail.com> wrote:
>> The way I see it the memory setup and SMP support in CAR are two very
>> different issues.
>
> This bug is totally my fault...
>
> Yes,  Memory setup and SMP CAR are two different issues. The SMP setup
> happens during CAR is to setup microcode, HT and FIDVID prior to the
> PLL reset and memory setup.
>
> All the SMP PCI config space access should be MMIO. It is the first
> thing that is enabled in CPU init in set_pci_mmio_conf_reg().
>
> The bug is that I mixed a mem setup function in with SMP setup by
> using mctGetLogicalCPUID() which uses Get_NB32. As pointed out, the
> GET_NB32 is a cf8/cfc function. The mct code ported from AGESA assumes
> that it is running on the BSP only and uses cf8/cfc..... (historical
> k8 bug I think)
>
> I think that I should change the mct PCI config functions to call the
> coreboot pci_read_config32 functions that handle MMIO vs cfc/cf8
> nicely. This should future proof  mct functions in CAR and a step
> toward SMP memory setup.
>
> Some of that mct code PCI config space code is a little funny (ok, a
> lot funny), so it will take a little care. I should be able work patch
> in a couple of days.


Here is a patch that fixes the cf8 config access. Not complicated like
I initially recalled.  Thanks to Ralf for pointing out the bug.

This needs testing. Anyone?

Signed-off-by: Marc Jones <marcj303@gmail.com>

Thanks,
Marc
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


Use the coreboot pci config read/write functions instead of direct cf8/cfc access. The fam10 pci functions will use mmio and not have  SMP pci access issues.

Signed-off-by: Marc Jones <marcj303@gmail.com↔

Index: coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c
===================================================================
--- coreboot-v2.orig/src/northbridge/amd/amdmct/mct/mct_d.c	2009-09-13 18:01:54.000000000 -0600
+++ coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c	2009-09-13 18:09:08.000000000 -0600
@@ -2474,10 +2474,8 @@
 {
 	u32 addr;
 
-	addr = (dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16);
-	outl((1<<31) | (addr & ~3), 0xcf8);
-
-	return inl(0xcfc);
+	addr = ((dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16)) & ~3;
+	return pci_read_config32(addr);
 }
 
 
@@ -2485,9 +2483,8 @@
 {
 	u32 addr;
 
-	addr = (dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16);
-	outl((1<<31) | (addr & ~3), 0xcf8);
-	outl(val, 0xcfc);
+	addr = ((dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16)) & ~3;
+	pci_write_config32(addr);
 }