===================================================================
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -32,9 +33,15 @@
device_t devfun3;
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
+ PCI_DEVICE_ID_VIA_K8T800_3, 0);
if (!devfun3)
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8M800_3, 0);
+ if (!devfun3)
+ devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
+ if (!devfun3)
+ devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
if (!devfun3)
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
@@ -108,16 +115,25 @@
device_t devfun7;
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
+ PCI_DEVICE_ID_VIA_K8T800_7, 0);
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8M800_7, 0);
+ if (!devfun7)
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
+ if (!devfun7)
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
/* No pairing NB was found. */
if (!devfun7)
+ {
+ print_debug("vt8237s_vlink_init: No pairing NB was found.\n");
return;
+ }
/*
* This init code is valid only for the VT8237S! For different
@@ -174,16 +190,25 @@
device_t devfun7;
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
+ PCI_DEVICE_ID_VIA_K8T800_7, 0);
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8M800_7, 0);
+ if (!devfun7)
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
+ if (!devfun7)
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
/* No pairing NB was found. */
if (!devfun7)
+ {
+ print_debug("vt8237a_vlink_init: No pairing NB was found.\n");
return;
+ }
/*
* This init code is valid only for the VT8237A! For different
===================================================================
@@ -1,3 +1,5 @@
+subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T800) += k8t890
+subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8M800) += k8t890
subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890
subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8M890) += k8t890
subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8231) += vt8231
===================================================================
@@ -33,7 +33,28 @@
* Below are some Dev0 Func2 HT control registers values,
* depending on strap pin, one of below lines is used.
*/
+#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800
+
tblpointer:
+.long 0x50220000, 0X619707C2
+.long 0x50220000, 0X619707C2
+.long 0x50220000, 0X619707C2
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+
+#elif CONFIG_SOUTHBRIDGE_VIA_K8890 || CONFIG_SOUTHBRIDGE_VIA_K8T890
+
+tblpointer:
.long 0x504400AA, 0x61970FC2 //;200M
.long 0x504400AA, 0x61970FC2 //;400M
.long 0x504400AA, 0x61970FC2 //;600M
@@ -50,6 +71,7 @@
.long 0x0
.long 0x0
+#endif
/*
* The pointer to above table should be at 0xffffd,
* the table itself MUST be aligned to 128B it seems!
===================================================================
@@ -1,3 +1,9 @@
+config SOUTHBRIDGE_VIA_K8M800 #K8M800 not tested
+ bool
+
+config SOUTHBRIDGE_VIA_K8T800
+ bool
+
config SOUTHBRIDGE_VIA_K8M890
bool
@@ -40,5 +46,5 @@
config ID_SECTION_OFFSET
hex
- default 0x80 if SOUTHBRIDGE_VIA_K8M890 || SOUTHBRIDGE_VIA_K8T890
+ default 0x80 if SOUTHBRIDGE_VIA_K8M890 || SOUTHBRIDGE_VIA_K8T890 || SOUTHBRIDGE_VIA_K8M800 || SOUTHBRIDGE_VIA_K8T800
===================================================================
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,12 +25,12 @@
#include <console/console.h>
#include <cbmem.h>
#include <arch/io.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
/* this may be later merged */
/* This fine tunes the HT link settings, which were loaded by ROM strap. */
-static void host_ctrl_enable_k8t890(struct device *dev)
+static void host_ctrl_enable_k8t8xx(struct device *dev)
{
dump_south(dev);
@@ -89,7 +90,7 @@
}
/* This fine tunes the HT link settings, which were loaded by ROM strap. */
-static void host_ctrl_enable_k8m890(struct device *dev) {
+static void host_ctrl_enable_k8m8xx(struct device *dev) {
/*
* Set PCI to HT outstanding requests to 03.
@@ -126,7 +127,7 @@
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .enable = host_ctrl_enable_k8t890,
+ .enable = host_ctrl_enable_k8t8xx,
.ops_pci = 0,
};
@@ -134,17 +135,29 @@
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .enable = host_ctrl_enable_k8m890,
+ .enable = host_ctrl_enable_k8m8xx,
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver_t __pci_driver = {
+static const struct pci_driver northbridge_driver_t800 __pci_driver = {
.ops = &host_ctrl_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T800_2,
+};
+
+static const struct pci_driver northbridge_driver_m800 __pci_driver = {
+ .ops = &host_ctrl_ops_m,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M800_2,
+};
+
+static const struct pci_driver northbridge_driver_t890 __pci_driver = {
+ .ops = &host_ctrl_ops_t,
+ .vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_2,
};
-static const struct pci_driver northbridge_driver_m __pci_driver = {
+static const struct pci_driver northbridge_driver_m890 __pci_driver = {
.ops = &host_ctrl_ops_m,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8M890CE_2,
===================================================================
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -25,7 +26,7 @@
#include <stdlib.h>
#include <cbmem.h>
#include <arch/io.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
/* The 256 bytes of NVRAM for S3 storage, 256B aligned */
#define K8T890_NVRAM_IO_BASE 0xf00
@@ -66,7 +67,15 @@
ldtnr = 2;
}
+#if defined(CONFIG_SOUTHBRIDGE_VIA_K8M800)
+ print_debug("K8M800 found at LDT ");
+#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T800)
+ print_debug("K8T800 found at LDT ");
+#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8M890)
+ print_debug("K8M890 found at LDT ");
+#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T890)
print_debug("K8T890 found at LDT ");
+#endif
print_debug_hex8(ldtnr);
/* get the maximum widths for both sides */
===================================================================
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -34,15 +35,26 @@
device_t devfun3;
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
+ PCI_DEVICE_ID_VIA_K8T800_3, 0);
if (!devfun3)
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8M800_3, 0);
+
+ if (!devfun3)
+ devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
+
+ if (!devfun3)
+ devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8T890CF_3, 0);
if (!devfun3)
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
+
+ if(!devfun3)
+ die(" vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n");
pci_write_config8(dev, 0x70, 0xc2);
@@ -113,6 +125,7 @@
static void vt8237r_vlink_init(struct device *dev)
{
u8 reg;
+ print_debug("K8x8xx: Initializing V-Link to VT8237R sb: ");
/*
* This init code is valid only for the VT8237R! For different
@@ -141,6 +154,7 @@
/* Program V-link 8X 16bit full duplex, parity enabled. */
pci_write_config8(dev, 0x48, 0xa3);
+ print_debug("Done\n");
}
static void ctrl_init(struct device *dev) {
@@ -173,19 +187,31 @@
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver_t __pci_driver = {
+static const struct pci_driver northbridge_driver_t800 __pci_driver = {
.ops = &ctrl_ops,
.vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T800_7,
+};
+
+static const struct pci_driver northbridge_driver_m800 __pci_driver = {
+ .ops = &ctrl_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M800_7,
+};
+
+static const struct pci_driver northbridge_driver_t890 __pci_driver = {
+ .ops = &ctrl_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_7,
};
-static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+static const struct pci_driver northbridge_driver_t890cf __pci_driver = {
.ops = &ctrl_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CF_7,
};
-static const struct pci_driver northbridge_driver_m __pci_driver = {
+static const struct pci_driver northbridge_driver_m890 __pci_driver = {
.ops = &ctrl_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8M890CE_7,
===================================================================
@@ -41,6 +41,7 @@
#ifdef __PRE_RAM__
u8 k8t890_early_setup_ht(void);
+#define k8x8xx_early_setup_ht() k8t890_early_setup_ht()
#else
#include <device/device.h>
#if 0
===================================================================
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -22,7 +23,7 @@
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
static void host_enable(struct device *dev)
{
@@ -70,19 +71,31 @@
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver_t __pci_driver = {
+static const struct pci_driver northbridge_driver_t800 __pci_driver = {
.ops = &host_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T800_0,
+};
+
+static const struct pci_driver northbridge_driver_m800 __pci_driver = {
+ .ops = &host_ops_m,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M800_0,
+};
+
+static const struct pci_driver northbridge_driver_t890 __pci_driver = {
+ .ops = &host_ops_t,
+ .vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_0,
};
-static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+static const struct pci_driver northbridge_driver_t890cf __pci_driver = {
.ops = &host_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CF_0,
};
-static const struct pci_driver northbridge_driver_m __pci_driver = {
+static const struct pci_driver northbridge_driver_m890 __pci_driver = {
.ops = &host_ops_m,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8M890CE_0,
===================================================================
@@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <string.h> /* for memset */
-#include "k8t890.h"
+#include "k8x8xx.h"
#if CONFIG_VGA
#include <pc80/vga_io.h>
@@ -169,6 +169,6 @@
static const struct pci_driver unichrome_driver __pci_driver = {
.ops = &chrome_ops,
- .vendor = 0x1106,
+ .vendor = PCI_VENDOR_ID_VIA,
.device = 0x3230,
};
===================================================================
@@ -138,6 +138,9 @@
.ops_pci = 0,
};
+/* K8X800 chipsets have no APIC; no 800 PCI ids here */
+
+
static const struct pci_driver northbridge_driver_t __pci_driver = {
.ops = &traf_ctrl_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
===================================================================
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -25,7 +26,7 @@
#include <cpu/amd/mtrr.h>
#include <pc80/mc146818rtc.h>
#include <bitops.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
static void dram_enable(struct device *dev)
{
@@ -110,6 +111,8 @@
k8m890_host_fb_size_get(void)
{
struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8M800_3, 0);
+ if(!dev) dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
unsigned char tmp;
@@ -164,19 +167,31 @@
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver_t __pci_driver = {
+static const struct pci_driver northbridge_driver_t800 __pci_driver = {
.ops = &dram_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T800_3,
+};
+
+static const struct pci_driver northbridge_driver_m800 __pci_driver = {
+ .ops = &dram_ops_m,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M800_3,
+};
+
+static const struct pci_driver northbridge_driver_t890 __pci_driver = {
+ .ops = &dram_ops_t,
+ .vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_3,
};
-static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+static const struct pci_driver northbridge_driver_t890cf __pci_driver = {
.ops = &dram_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CF_3,
};
-static const struct pci_driver northbridge_driver_m __pci_driver = {
+static const struct pci_driver northbridge_driver_m890 __pci_driver = {
.ops = &dram_ops_m,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8M890CE_3,
===================================================================
@@ -0,0 +1,25 @@
+ /*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H
+#define SOUTHBRIDGE_VIA_K8T890_K8X8XX_H
+
+#include "k8t890.h"
+
+#endif//SOUTHBRIDGE_VIA_K8T890_K8X8XX_H
\ No newline at end of file
===================================================================
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,6 +25,7 @@
static void error_enable(struct device *dev)
{
+ print_debug(" K8x8xx: Enabling V-Link error reporting: ");
/*
* bit0 - Enable V-link parity error reporting in 0x50 bit0 (RWC)
* bit6 - Parity Error/SERR# Report Through V-Link to SB
@@ -31,6 +33,7 @@
*/
pci_write_config8(dev, 0x58, 0x81);
+ print_debug("Done\n");
/* TODO: enable AGP errors reporting on K8M890 */
}
@@ -42,9 +45,15 @@
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver_t __pci_driver = {
+static const struct pci_driver northbridge_driver_t800 __pci_driver = {
.ops = &error_ops,
.vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T800_1,
+};
+
+static const struct pci_driver northbridge_driver_t890 __pci_driver = {
+ .ops = &error_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_1,
};
===================================================================
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@@ -21,7 +21,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <console/console.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
static void bridge_enable(struct device *dev)
{
@@ -63,8 +63,14 @@
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver __pci_driver = {
+static const struct pci_driver northbridge_driver_800 __pci_driver = {
.ops = &bridge_ops,
.vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T800_BR,
+};
+
+static const struct pci_driver northbridge_driver_890 __pci_driver = {
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_BR,
-};
+};
\ No newline at end of file
===================================================================
@@ -183,6 +183,13 @@
step = 1 << gran;
/* Find the first bit that moves. */
+ /* Find the first bit that moves. */
+ /* If by any chance, moving will be zero when entering the loop
+ * we will never exit it. This check ensures that execution
+ * continues if this conditon arises.
+ * FIXME: Is this the best solution?
+ */
+ if(moving != 0)
while ((moving & step) == 0) {
gran--;
step >>= 1;
===================================================================
@@ -1220,6 +1220,24 @@
#define PCI_DEVICE_ID_VIA_8505_1 0x8605
#define PCI_DEVICE_ID_VIA_8633_1 0xB091
#define PCI_DEVICE_ID_VIA_8367_1 0xB099
+#define PCI_DEVICE_ID_VIA_K8T800_0 0x0282
+#define PCI_DEVICE_ID_VIA_K8T800_1 0x1282
+#define PCI_DEVICE_ID_VIA_K8T800_2 0x2282
+#define PCI_DEVICE_ID_VIA_K8T800_3 0x3282
+#define PCI_DEVICE_ID_VIA_K8T800_4 0x4282
+#define PCI_DEVICE_ID_VIA_K8T800_5 0x5282
+#define PCI_DEVICE_ID_VIA_K8T800_6 0x6282
+#define PCI_DEVICE_ID_VIA_K8T800_7 0x7282
+#define PCI_DEVICE_ID_VIA_K8M800_0 0x0204
+#define PCI_DEVICE_ID_VIA_K8M800_1 0x1204
+#define PCI_DEVICE_ID_VIA_K8M800_2 0x2204
+#define PCI_DEVICE_ID_VIA_K8M800_3 0x3204
+#define PCI_DEVICE_ID_VIA_K8M800_4 0x4204
+#define PCI_DEVICE_ID_VIA_K8M800_5 0x5204
+#define PCI_DEVICE_ID_VIA_K8M800_6 0x6204
+#define PCI_DEVICE_ID_VIA_K8M800_7 0x7204
+#define PCI_DEVICE_ID_VIA_K8T800_AGP 0x3188
+#define PCI_DEVICE_ID_VIA_K8T800_BR 0xb188
#define PCI_DEVICE_ID_VIA_K8T890CE_0 0x0238
#define PCI_DEVICE_ID_VIA_K8T890CE_1 0x1238
#define PCI_DEVICE_ID_VIA_K8T890CE_2 0x2238
===================================================================
@@ -27,6 +27,8 @@
bool "A8V-E SE"
config BOARD_ASUS_A8V_E_DELUXE
bool "A8V-E Deluxe"
+config BOARD_ASUS_K8V_X_SE
+ bool "K8V-X SE"
config BOARD_ASUS_M2N_E
bool "M2N-E"
config BOARD_ASUS_M2V
@@ -59,6 +61,7 @@
source "src/mainboard/asus/a8n_e/Kconfig"
source "src/mainboard/asus/a8v-e_se/Kconfig"
source "src/mainboard/asus/a8v-e_deluxe/Kconfig"
+source "src/mainboard/asus/k8v-x_se/Kconfig"
source "src/mainboard/asus/m2n-e/Kconfig"
source "src/mainboard/asus/m2v/Kconfig"
source "src/mainboard/asus/m2v-mx_se/Kconfig"
===================================================================
@@ -0,0 +1,76 @@
+if BOARD_ASUS_K8V_X_SE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_AMD_SOCKET_754
+ select NORTHBRIDGE_AMD_AMDK8
+ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+ select SOUTHBRIDGE_VIA_VT8237R
+ select SOUTHBRIDGE_VIA_K8T800
+ select SUPERIO_WINBOND_W83627EHG
+ select CACHE_AS_RAM
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_TABLES
+ select HAVE_MP_TABLE
+ select BOARD_ROMSIZE_KB_512
+ select RAMINIT_SYSINFO
+ select QRANK_DIMM_SUPPORT
+
+config MAINBOARD_DIR
+ string
+ default asus/k8v-x_se
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xcc000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x4000
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+ hex
+ default 0x1000
+
+config APIC_ID_OFFSET
+ hex
+ default 0x10
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 1
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "K8V-X SE"
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0
+
+config MAX_CPUS
+ int
+ default 2
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 1
+
+config HEAP_SIZE
+ hex
+ default 0x40000
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x20
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0x0
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1043
+
+endif # BOARD_ASUS_K8V_X_SE
===================================================================
@@ -0,0 +1,224 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 AMD
+ * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
+ * Copyright (C) 2006 MSI
+ * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+unsigned int get_sbdn(unsigned bus);
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+#include "superio/winbond/w83627ehg/early_serial.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
+#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include <spd.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
+#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
+
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include <reset.h>
+void soft_reset(void)
+{
+ uint8_t tmp;
+
+ set_bios_reset();
+ print_debug("soft reset \n");
+
+ /* PCI reset */
+ tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
+ tmp |= 0x01;
+ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
+
+ while (1) {
+ /* daisy daisy ... */
+ hlt();
+ }
+}
+
+#include "southbridge/via/k8t890/early_car.c"
+#include "northbridge/amd/amdk8/amdk8.h"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/raminit.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/dualcore/dualcore.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+//#include "cpu/amd/model_fxx/fidvid.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
+
+unsigned int get_sbdn(unsigned bus)
+{
+ device_t dev;
+
+ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
+ return (dev >> 15) & 0x1f;
+}
+
+static void sio_init(void)
+{
+ u8 reg;
+
+ pnp_enter_ext_func_mode(SERIAL_DEV);
+ /* We have 24MHz input. */
+ reg = pnp_read_config(SERIAL_DEV, 0x24);
+ pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
+ /* We have GPIO for KB/MS pin. */
+ reg = pnp_read_config(SERIAL_DEV, 0x2a);
+ pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
+ /* We have all RESTOUT and even some reserved bits, too. */
+ reg = pnp_read_config(SERIAL_DEV, 0x2c);
+ pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
+ pnp_exit_ext_func_mode(SERIAL_DEV);
+
+ pnp_enter_ext_func_mode(ACPI_DEV);
+ pnp_set_logical_device(ACPI_DEV);
+ /*
+ * Set the delay rising time from PWROK_LP to PWROK_ST to
+ * 300 - 600ms, and 0 to vice versa.
+ */
+ reg = pnp_read_config(ACPI_DEV, 0xe6);
+ pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
+ /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
+ reg = pnp_read_config(ACPI_DEV, 0xe4);
+ pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
+ pnp_exit_ext_func_mode(ACPI_DEV);
+
+ pnp_enter_ext_func_mode(GPIO_DEV);
+ pnp_set_logical_device(GPIO_DEV);
+ /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
+ pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
+ pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
+ pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
+ pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */
+ pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */
+ pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
+ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
+ pnp_exit_ext_func_mode(GPIO_DEV);
+}
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ static const uint16_t spd_addr[] = {
+ // Node 0
+ DIMM0, DIMM1, 0, 0,
+ };
+ unsigned bsp_apicid = 0;
+ int needs_reset = 0;
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+ sio_init();
+ w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ uart_init();
+ console_init();
+ enable_rom_decode();
+
+ print_info("now booting... fallback\n");
+
+ /* Is this a CPU only reset? Or is this a secondary CPU? */
+ if (!cpu_init_detectedx && boot_cpu()) {
+ /* Nothing special needs to be done to find bus 0. */
+ /* Allow the HT devices to be found. */
+ enumerate_ht_chain();
+ }
+
+ sio_init();
+ w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ uart_init();
+ console_init();
+ enable_rom_decode();
+
+ print_info("now booting... real_main\n");
+
+ if (bist == 0)
+ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+
+ /* Halt if there was a built in self test failure. */
+ report_bist_failure(bist);
+
+ setup_default_resource_map();
+ setup_coherent_ht_domain();
+ wait_all_core0_started();
+
+ print_info("now booting... Core0 started\n");
+
+#if CONFIG_LOGICAL_CPUS==1
+ /* It is said that we should start core1 after all core0 launched. */
+ start_other_cores();
+ wait_all_other_cores_started(bsp_apicid);
+#endif
+ init_timer();
+ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
+
+ needs_reset = optimize_link_coherent_ht();
+ needs_reset |= optimize_link_incoherent_ht(sysinfo);
+ needs_reset |= k8x8xx_early_setup_ht();
+
+ if (needs_reset) {
+ print_debug("ht reset -\n");
+ //soft_reset();
+ }
+
+ /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
+ /*enable_fid_change();
+ print_debug("post fis_change\n");
+ init_fidvid_bsp(bsp_apicid);
+ */
+
+ /* Stop the APs so we can start them later in init. */
+ allow_all_aps_stop(bsp_apicid);
+
+ /* It's the time to set ctrl now. */
+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+ enable_smbus();
+ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+ post_cache_as_ram();
+}
===================================================================
@@ -0,0 +1,92 @@
+chip northbridge/amd/amdk8/root_complex # Root complex
+ device lapic_cluster 0 on # APIC cluster
+ chip cpu/amd/socket_754 # CPU
+ device lapic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ chip northbridge/amd/amdk8 # mc0
+ device pci 18.0 on # Northbridge
+ # Devices on link 0, link 0 == LDT 0
+ chip southbridge/via/vt8237r # Southbridge
+ register "ide0_enable" = "1" # Enable IDE channel 0
+ register "ide1_enable" = "1" # Enable IDE channel 1
+ register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
+ register "ide1_80pin_cable" = "0" # 80pin cable on IDE channel 1
+ register "fn_ctrl_lo" = "0" # Enable SB functions
+ register "fn_ctrl_hi" = "0xad" # Enable SB functions
+ device pci 0.0 on end # HT
+ device pci f.1 on end # IDE
+ device pci 11.0 on # LPC
+ chip drivers/generic/generic # DIMM 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic # DIMM 0-0-1
+ device i2c 51 on end
+ end
+ chip superio/winbond/w83627ehg # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 4
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2 (N/A on this board)
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # PS/2 keyboard & mouse (on or off?)
+ io 0x60 = 0x60
+ irq 0x70 = 1
+ end
+ device pnp 2e.106 off # Serial flash interface (SFI)
+ io 0x60 = 0x100
+ end
+ device pnp 2e.007 off # GPIO 1
+ end
+ device pnp 2e.107 off # Game port
+ io 0x60 = 0x201
+ end
+ device pnp 2e.207 off # MIDI
+ io 0x62 = 0x330
+ irq 0x70 = 9
+ end
+ device pnp 2e.307 off # GPIO 6
+ end
+ device pnp 2e.8 off # WDTO#, PLED
+ end
+ device pnp 2e.009 on # GPIO 2
+ end
+ device pnp 2e.109 off # GPIO 3
+ end
+ device pnp 2e.209 off # GPIO 4
+ end
+ device pnp 2e.309 on # GPIO 5
+ end
+ device pnp 2e.a off # ACPI
+ end
+ device pnp 2e.b on # Hardware monitor
+ io 0x60 = 0x290
+ irq 0x70 = 0
+ end
+ end
+ end
+ device pci 12.0 on end # VIA LAN
+ end
+ chip southbridge/via/k8t800 # "Southbridge" K8T800
+ end
+ end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
===================================================================
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+/* generated by MPTable, version 2.0.15*/
+/* as modified by RGM for coreboot */
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+#include "southbridge/via/vt8237r/vt8237r.h"
+#include "southbridge/via/k8t890/k8x8xx.h"
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LAPIC_ADDR);
+
+ smp_write_processors(mc);
+
+
+ /*Bus: Bus ID Type*/
+ /*smp_write_bus(mc, 0, "PCI ");
+ smp_write_bus(mc, 1, "PCI ");
+ smp_write_bus(mc, 2, "ISA ");*/
+ /*I/O APICs: APIC ID Version State Address*/
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
+ /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
+ */
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x0, 0x1, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x1, 0x1, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x0, 0x1, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x3, 0x1, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x4, 0x1, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x5, 0x1, 0x5);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x6, 0x1, 0x6);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x7, 0x1, 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x2, 0x8, 0x1, 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x9, 0x1, 0x9);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xa, 0x1, 0xa);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xb, 0x1, 0xb);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xc, 0x1, 0xc);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xd, 0x1, 0xd);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xe, 0x1, 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xf, 0x1, 0xf);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x1, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x46, 0x1, 0x16);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x1, 0x14);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3c, 0x1, 0x14);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x1, 0x15);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x1, 0x15);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x1, 0x15);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x2c, 0x1, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x30, 0x1, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x1, 0x17);
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
+ /* Compute the checksums. */
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
+
===================================================================
@@ -0,0 +1,134 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Written by Stefan Reinauer <stepan@openbios.org>.
+ * ACPI FADT, FACS, and DSDT table support added by
+ *
+ * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
+ * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include "southbridge/via/vt8237r/vt8237r.h"
+#include "southbridge/via/k8t890/k8x8xx.h"
+
+extern const unsigned char AmlCode[];
+
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ return 0;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Create all subtables for processors. */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write SB IOAPIC. */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ VT8237R_APIC_ID, IO_APIC_ADDR, 0);
+
+ /* IRQ9 ACPI active low. */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
+
+ /* IRQ0 -> APIC IRQ2. */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0x0);
+
+ /* Create all subtables for processors. */
+ current = acpi_create_madt_lapic_nmis(current,
+ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
+
+ return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_srat_t *srat;
+ acpi_rsdt_t *rsdt;
+ acpi_madt_t *madt;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+
+ /* Align ACPI tables to 16 byte. */
+ start = (start + 0x0f) & -0x10;
+ current = start;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT table. */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* Clear all table memory. */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /* We explicitly add these tables later on: */
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ dsdt = (acpi_header_t *)current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ dsdt->checksum = 0; /* Don't trust iasl to get this right. */
+ dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /* If we want to use HPET timers Linux wants it in MADT. */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ acpi_add_table(rsdp, madt);
+
+ printk(BIOS_DEBUG, "ACPI: * SRAT\n");
+ srat = (acpi_srat_t *) current;
+ acpi_create_srat(srat);
+ current += srat->header.length;
+ acpi_add_table(rsdp, srat);
+
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
===================================================================
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
===================================================================
@@ -0,0 +1,148 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
+{
+ /* Define the main processor.*/
+ Scope (\_PR)
+ {
+ Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
+ }
+
+ /* For now only define 2 power states:
+ * - S0 which is fully on
+ * - S5 which is soft off
+ * Any others would involve declaring the wake up methods.
+ */
+ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+ Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
+
+ /* Root of the bus hierarchy */
+ Scope (\_SB)
+ {
+ /* Top PCI device */
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x00)
+
+ /* PCI Routing Table */
+ /* aaa */
+ Name (_PRT, Package () {
+ Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xA */
+ Package (0x04) { 0x000AFFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x000AFFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x000AFFFF, 0x03, 0x00, 0x13 },
+ Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xB */
+ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x13 },
+ Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x10 },
+ Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xC */
+ Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x13 },
+ Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x10 },
+ Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x11 },
+ Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xD */
+ Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x10 },
+ Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x11 },
+ Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x12 },
+ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
+ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
+ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
+ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
+ Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
+ Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
+ Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
+ Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
+ })
+
+ Device (ISA) {
+ Name (_ADR, 0x00110000)
+
+ /* PS/2 keyboard (seems to be important for WinXP install) */
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 floppy controller */
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () {
+ IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+ IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+ IRQNoFlags () {6}
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}
+ })
+ Return (BUF0)
+ }
+ }
+ }
+ }
+ }
+}
===================================================================
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 DDR400
+8 1 DDR333
+8 2 DDR266
+8 3 DDR200
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
+
+
===================================================================
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS K8V_X SE Mainboard")
+};
Added preliminary support for the ASUS K8V-X SE and the VIA K8T800 chipset. Coreboot is able to finalize and load SeaBIOS, which boots from IDE HDD or DVD. IRQ ACPI and MP tables are not yet complete. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> --- I've refined the previous patch with the help of ruik (on #coreboot IRC). This is still a work in progress. As of right now, USB does not work, and linux freezes on boot, IRQ routing is a mess. Alex