AMDMCT DDR3 fix Dual rank + high mem frequency.

Submitter	Bao, Zheng
Date	2011-01-19 09:37:44
Message ID	<DD1CC71B621B004FA76856E5129D6B170474C670@sbjgexmb1.amd.com>
Download	mbox \| patch
Permalink	/patch/2536/
State	New
Headers	show Return-path: <coreboot-bounces@coreboot.org> Envelope-to: patchwork@coreboot.org Content-Class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----_=_NextPart_001_01CBB7BC.86E537E6" Date: Wed, 19 Jan 2011 17:37:44 +0800 Message-ID: <DD1CC71B621B004FA76856E5129D6B170474C670@sbjgexmb1.amd.com> Thread-Index: Acu3vIZc3DP5PgM7RqK5H1AfJQkz+w== From: "Bao, Zheng" <Zheng.Bao@amd.com> To: <coreboot@coreboot.org> Subject: [coreboot] [patch] AMDMCT DDR3 fix Dual rank + high mem frequency. Precedence: list Sender: coreboot-bounces@coreboot.org Errors-To: coreboot-bounces@coreboot.org

Comments

Bao, Zheng - 2011-01-19 09:37:44

For Cx, each ChipSel need to be sent MR command.
After this patch, tilapia can run in higher memory frequency.
To test the high frequency, dont forget to change the freq limit in
mcti_d.c:
 static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
 {
	 pDCTstat->PresetmaxFreq = 800;
 }

Signed-off-by: Zheng Bao <zheng.bao@amd.com>

*/)) /* We dont support RB_C0 now. need to be added and tested. */
 			if (!(pDCTstat->Status & (1 << SB_Registered)))
 				MrsChipSel ++;
 	}
For Cx, each ChipSel need to be sent MR command.
After this patch, tilapia can run in higher memory frequency.
To test the high frequency, dont forget to change the freq limit in
mcti_d.c:
 static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
 {
	 pDCTstat->PresetmaxFreq = 800;
 }

Signed-off-by: Zheng Bao <zheng.bao@amd.com>

Stefan Reinauer - 2011-01-19 18:35:48

* Bao, Zheng <Zheng.Bao@amd.com> [110119 10:37]:
> For Cx, each ChipSel need to be sent MR command.
> After this patch, tilapia can run in higher memory frequency.
> To test the high frequency, dont forget to change the freq limit in
> mcti_d.c:
>  static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
>  {
> 	 pDCTstat->PresetmaxFreq = 800;
>  }

Is it safe to add this to the repository? I'm worried that people will
forget over time.

> Signed-off-by: Zheng Bao <zheng.bao@amd.com>
 
Acked-by: Stefan Reinauer <stepan@coreboot.org>

> Index: src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
> ===================================================================
> --- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c	(revision 6275)
> +++ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c	(working copy)
> @@ -306,7 +306,7 @@
>  				if (!(pDCTstat->Status & (1 <<
> SB_Registered)))
>  					break; /* For UDIMM, only send
> MR commands once per channel */
>  		}
> -		if (pDCTstat->LogicalCPUID & (AMD_DR_Cx/* | AMD_RB_C0
> */)) /* We dont support RB_C0 now. need to be added and tested. */
> +		if (pDCTstat->LogicalCPUID & (AMD_DR_Bx/* | AMD_RB_C0
> */)) /* We dont support RB_C0 now. need to be added and tested. */
>  			if (!(pDCTstat->Status & (1 << SB_Registered)))
>  				MrsChipSel ++;
>  	}


> -- 
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

Bao, Zheng - 2011-01-20 02:01:36

I think we need a report table to record the status of every combination
of processor + DIMMs. More test need to be done on the supported boards.
We can not change PresetmaxFreq to 800 until it is ok for each case.
Before that, I am afraid we need to keep in mind that there is a limit
here.


Zheng

> -----Original Message-----
> From: Stefan Reinauer [mailto:stefan.reinauer@coreboot.org]
> Sent: Thursday, January 20, 2011 2:36 AM
> To: Bao, Zheng
> Cc: coreboot@coreboot.org
> Subject: Re: [coreboot] [patch] AMDMCT DDR3 fix Dual rank + high mem
> frequency.
> 
> * Bao, Zheng <Zheng.Bao@amd.com> [110119 10:37]:
> > For Cx, each ChipSel need to be sent MR command.
> > After this patch, tilapia can run in higher memory frequency.
> > To test the high frequency, dont forget to change the freq limit in
> > mcti_d.c:
> >  static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
> >  {
> > 	 pDCTstat->PresetmaxFreq = 800;
> >  }
> 
> Is it safe to add this to the repository? I'm worried that people will
> forget over time.
> 
> > Signed-off-by: Zheng Bao <zheng.bao@amd.com>
> 
> Acked-by: Stefan Reinauer <stepan@coreboot.org>
> 
> > Index: src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
> > ===================================================================
> > --- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c	(revision 6275)
> > +++ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c	(working copy)
> > @@ -306,7 +306,7 @@
> >  				if (!(pDCTstat->Status & (1 <<
> > SB_Registered)))
> >  					break; /* For UDIMM, only send
> > MR commands once per channel */
> >  		}
> > -		if (pDCTstat->LogicalCPUID & (AMD_DR_Cx/* | AMD_RB_C0
> > */)) /* We dont support RB_C0 now. need to be added and tested. */
> > +		if (pDCTstat->LogicalCPUID & (AMD_DR_Bx/* | AMD_RB_C0
> > */)) /* We dont support RB_C0 now. need to be added and tested. */
> >  			if (!(pDCTstat->Status & (1 << SB_Registered)))
> >  				MrsChipSel ++;
> >  	}
> 
> 
> > --
> > coreboot mailing list: coreboot@coreboot.org
> > http://www.coreboot.org/mailman/listinfo/coreboot
>

Patch

Index: src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
===================================================================
--- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c	(revision 6275)
+++ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c	(working copy)
@@ -306,7 +306,7 @@ 
 				if (!(pDCTstat->Status & (1 << SB_Registered)))
 					break; /* For UDIMM, only send MR commands once per channel */
 		}
-		if (pDCTstat->LogicalCPUID & (AMD_DR_Cx/* | AMD_RB_C0 */)) /* We dont support RB_C0 now. need to be added and tested. */
+		if (pDCTstat->LogicalCPUID & (AMD_DR_Bx/* | AMD_RB_C0 */)) /* We dont support RB_C0 now. need to be added and tested. */
 			if (!(pDCTstat->Status & (1 << SB_Registered)))
 				MrsChipSel ++;
 	}

Patchwork AMDMCT DDR3 fix Dual rank + high mem frequency.

Comments

Patch