From patchwork Fri Jan 28 21:31:12 2011
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Subject: Fix LPC decode ranges on SB700
Date: Fri, 28 Jan 2011 21:31:12 -0000
From: Rudolf Marek <r.marek@assembler.cz>
X-Patchwork-Id: 2577
Message-Id: <4D4335A0.8030809@assembler.cz>
To: Marc Jones <marcj303@gmail.com>
Cc: Stefan Reinauer <stefan.reinauer@coreboot.org>,
 Coreboot <coreboot@coreboot.org>

Oh yes seems it is quite similar. I could not test this, I'm attaching the changes.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>

Thanks,
Rudolf
Acked-by: Marc Jones <marcj303@gmail.com>


Index: src/southbridge/amd/sb800/lpc.c
===================================================================
--- src/southbridge/amd/sb800/lpc.c	(revision 6315)
+++ src/southbridge/amd/sb800/lpc.c	(working copy)
@@ -122,7 +122,8 @@
 	struct bus *link;
 	u32 reg, reg_x;
 	int var_num = 0;
-	u16 reg_var[3];
+	u16 reg_var[3] = {0x0, 0x0, 0x0};
+	u8 wiosize = pci_read_config8(dev, 0x74);
 
 	reg = pci_read_config32(dev, 0x44);
 	reg_x = pci_read_config32(dev, 0x48);
@@ -153,13 +154,14 @@
 					case 0x2f8:	/*  COM2 */
 						reg |= (1 << 7);
 						break;
-					case 0x378:	/*  Parallal 1 */
+					case 0x378:	/*  Parallel 1 */
 						reg |= (1 << 0);
+						reg |= (1 << 1); /* + 0x778for ECP */
 						break;
 					case 0x3f0:	/*  FD0 */
 						reg |= (1 << 26);
 						break;
-					case 0x220:	/*  Aduio 0 */
+					case 0x220:	/*  Audio 0 */
 						reg |= (1 << 8);
 						break;
 					case 0x300:	/*  Midi 0 */
@@ -189,12 +191,19 @@
 						switch (var_num) {
 						case 0:
 							reg_x |= (1 << 2);
+							if ((end - base) < 16)
+								wiosize |= (1 << 0);
 							break;
 						case 1:
 							reg_x |= (1 << 24);
+							if ((end - base) < 16)
+								wiosize |= (1 << 2);
 							break;
 						case 2:
 							reg_x |= (1 << 25);
+							reg_x |= (1 << 24);
+							if ((end - base) < 16)
+								wiosize |= (1 << 3);
 							break;
 						}
 						reg_var[var_num++] =
@@ -216,6 +225,7 @@
 		pci_write_config16(dev, 0x64, reg_var[0]);
 		break;
 	}
+	pci_write_config8(dev, 0x74, wiosize);
 }
 
 static void sb800_lpc_enable_resources(device_t dev)
Index: src/southbridge/amd/sb800/early_setup.c
===================================================================
--- src/southbridge/amd/sb800/early_setup.c	(revision 6315)
+++ src/southbridge/amd/sb800/early_setup.c	(working copy)
@@ -450,26 +450,8 @@
 	/* DMA enable */
 	pci_write_config8(dev, 0x40, 0x04);
 
-	/* IO Port Decode Enable */
-	pci_write_config8(dev, 0x44, 0xFF);
-	pci_write_config8(dev, 0x45, 0xFF);
-	pci_write_config8(dev, 0x46, 0xC3);
-	pci_write_config8(dev, 0x47, 0xFF);
-
-	/* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
-	 *  Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f),
-	 * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65).
-	 * Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/
-	byte = pci_read_config8(dev, 0x48);
-	byte |= (1 << 1) | (1 << 0);	/* enable Super IO config port 2e-2h, 4e-4f */
-	byte |= (1 << 3) | (1 << 4);	/* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */
-	byte |= 1 << 6;		/* enable for RTC I/O range */
-	pci_write_config8(dev, 0x48, byte);
+	/* LPC Sync Timeout */
 	pci_write_config8(dev, 0x49, 0xFF);
-	/* Enable 0x480-0x4bf, 0x4700-0x470B */
-	byte = pci_read_config8(dev, 0x4A);
-	byte |= ((1 << 1) + (1 << 6));	/*0x42, save the configuraion for port 0x80. */
-	pci_write_config8(dev, 0x4A, byte);
 
 	/* Set LPC ROM size, it has been done in sb800_lpc_init().
 	 * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;