Patchwork Fix some errata for AMD Family F processors

login
register
about
Submitter Alexandru Gagniuc
Date 2011-02-08 21:40:06
Message ID <4D51B836.9070700@gmail.com>
Download mbox | patch
Permalink /patch/2618/
State Accepted
Headers show

Comments

Alexandru Gagniuc - 2011-02-08 21:40:06
On 02/08/2011 11:37 PM, Alex G. wrote:
> See patch for detailed description.
> 
> Alex

I should really attach the patch first before writing anything. Sorry
about that. Here's the patch.

Alex

Patch

Implemented workaround fot erratum 169, obsoleting errattum 131.
Workaround for 131 removed.
Changed erratum 89 workaround to include revision F processors.
Changed workaround for erratum 110 to only include pre-revision_f
processors.

For details, check AMD publications:
#25759 (Errata for Fam F pre-revision F processors)
#33610 (Errata for Fam F revision F and later processor)

Based on work and previous patches by:
Rudolf Marek <r.marek@assembler.cz> 
Josef Kellermann <seppk@arcor.de>

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

Index: src/cpu/amd/model_fxx/model_fxx_init.c
===================================================================
--- src/cpu/amd/model_fxx/model_fxx_init.c	(revision 6336)
+++ src/cpu/amd/model_fxx/model_fxx_init.c	(working copy)
@@ -384,24 +384,7 @@ 
 		wrmsr_amd(DC_CFG_MSR, msr);
 
 	}
-	/* I can't touch this msr on early buggy cpus */
-	if (!is_cpu_pre_b3()) {
 
-		/* Erratum 89 ... */
-		msr = rdmsr(NB_CFG_MSR);
-		msr.lo |= 1 << 3;
-
-		if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
-			/* D0 later don't need it */
-			/* Erratum 86 Disable data masking on C0 and
-			 * later processor revs.
-			 * FIXME this is only needed if ECC is enabled.
-			 */
-			msr.hi |= 1 << (36 - 32);
-		}
-		wrmsr(NB_CFG_MSR, msr);
-	}
-
 	/* Erratum 97 ... */
 	if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
 		msr = rdmsr_amd(DC_CFG_MSR);
@@ -428,35 +411,64 @@ 
 	msr.hi |= 1 << (43 - 32);
 	wrmsr_amd(BU_CFG_MSR, msr);
 
+	/* Erratum 110 */
+	/* This erratum applies to D0 thru E6 revisions
+	 * Revision F and later are unaffected. There are two fixes
+	 * depending on processor revision.
+	 */
 	if (is_cpu_d0()) {
 		/* Erratum 110 ... */
 		msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
 		msr.hi |= 1;
 		wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
 	}
-#endif
 
-#if CONFIG_K8_REV_F_SUPPORT == 0
 	if (!is_cpu_pre_e0())
-#endif
 	{
 		/* Erratum 110 ... */
 		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
 		msr.hi |= 1;
 		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
 	}
+#endif
 
+
+#if CONFIG_K8_REV_F_SUPPORT == 0
+	/* I can't touch this msr on early buggy cpus */
+	if (!is_cpu_pre_b3())
+#endif
+	{
+		msr = rdmsr(NB_CFG_MSR);
+		
+#if CONFIG_K8_REV_F_SUPPORT == 0
+		if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
+			/* D0 later don't need it */
+			/* Erratum 86 Disable data masking on C0 and
+			 * later processor revs.
+			 * FIXME this is only needed if ECC is enabled.
+			 */
+			msr.hi |= 1 << (36 - 32);
+		}
+#endif
+		/* Erratum 89 ... */
+		/* Erratum 89 is mistakenly labeled as 88 in AMD pub #25759
+		 * It is correctly labeled as 89 on page 49 of the document
+		 * and in AMD pub#33610
+		 */
+		msr.lo |= 1 << 3;
+		/* Erratum 169 */
+		/* This supersedes erratum 131; 131 should not be applied with 169 
+		 * We also need to set some bits in the northbridge, handled in src/northbridge/amdk8/
+		 */
+		msr.hi |= 1;
+		
+		wrmsr(NB_CFG_MSR, msr);
+	}
 	/* Erratum 122 */
 	msr = rdmsr(HWCR_MSR);
 	msr.lo |= 1 << 6;
 	wrmsr(HWCR_MSR, msr);
 
-#if CONFIG_K8_REV_F_SUPPORT == 1
-	/* Erratum 131... */
-	msr = rdmsr(NB_CFG_MSR);
-	msr.lo |= 1 << 20;
-	wrmsr(NB_CFG_MSR, msr);
-#endif
 
 }
 
Index: src/northbridge/amd/amdk8/coherent_ht.c
===================================================================
--- src/northbridge/amd/amdk8/coherent_ht.c	(revision 6336)
+++ src/northbridge/amd/amdk8/coherent_ht.c	(working copy)
@@ -1662,10 +1662,10 @@ 
 	unsigned node;
 	int needs_reset = 0;
 	for(node = 0; node < nodes; node++) {
-#if CONFIG_K8_REV_F_SUPPORT == 0
 		device_t dev;
 		uint32_t cmd;
 		dev = NODE_MC(node);
+#if CONFIG_K8_REV_F_SUPPORT == 0
 		if (is_cpu_pre_c0()) {
 
 			/* Errata 66
@@ -1708,6 +1708,20 @@ 
 			}
 		}
 #endif
+
+		
+#if CONFIG_K8_REV_F_SUPPORT == 0
+		/* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
+		if (!is_cpu_pre_b3())
+#endif
+		{
+			/* Errata 169 */
+			/* We also need to set some bits in NB_CFG_MSR, which is handled in src/cpu/amd/model_fxx/ */
+			cmd = pci_read_config32(dev, 0x68);
+			cmd &= ~(1 << 22);
+			cmd |= (1 << 21);
+			pci_write_config32(dev, 0x68, cmd);
+		}
 	}
 	return needs_reset;
 }