| Submitter | Scott |
|---|---|
| Date | 2011-02-10 19:32:31 |
| Message ID | <46BB7DA45F6A4D8F85B38E0F7EC230A1@m3a78> |
| Download | mbox | patch |
| Permalink | /patch/2619/ |
| State | Accepted |
| Commit | r6342 |
| Headers | show |
Comments
On Thu, Feb 10, 2011 at 12:32 PM, Scott Duplichan <scott@notabs.org> wrote: > According to AMD documentation, cache type WP should be used for > execution from flash memory. Coreboot uses WB. While there is no > noticeable performance difference between the two settings, use > of WB can cause a problem for a jtag debugger. The attached > patch changes AMD cache as ram setting for flash execution from > WB to WP. > > Signed-off-by: Scott Duplichan <scott@notabs.org> > > Index: src/cpu/amd/car/cache_as_ram.inc > =================================================================== > --- src/cpu/amd/car/cache_as_ram.inc (revision 6341) > +++ src/cpu/amd/car/cache_as_ram.inc (working copy) > @@ -294,11 +294,11 @@ > xorl %edx, %edx > /* > * IMPORTANT: The two lines below can _not_ be written like this: > - * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax > + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax > * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html > */ > movl $REAL_XIP_ROM_BASE, %eax > - orl $MTRR_TYPE_WRBACK, %eax > + orl $MTRR_TYPE_WRPROT, %eax > wrmsr > > movl $MTRRphysMask_MSR(1), %ecx > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > Acked-by: Marc Jones <marcj303@gmail.com>
Patch
Index: src/cpu/amd/car/cache_as_ram.inc =================================================================== --- src/cpu/amd/car/cache_as_ram.inc (revision 6341) +++ src/cpu/amd/car/cache_as_ram.inc (working copy) @@ -294,11 +294,11 @@ xorl %edx, %edx /* * IMPORTANT: The two lines below can _not_ be written like this: - * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $REAL_XIP_ROM_BASE, %eax - orl $MTRR_TYPE_WRBACK, %eax + orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx
According to AMD documentation, cache type WP should be used for execution from flash memory. Coreboot uses WB. While there is no noticeable performance difference between the two settings, use of WB can cause a problem for a jtag debugger. The attached patch changes AMD cache as ram setting for flash execution from WB to WP. Signed-off-by: Scott Duplichan <scott@notabs.org>