From patchwork Thu Feb 10 19:32:31 2011
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Subject: cache type for BIOS flash memory should be WP-MMIO, not WB-MMIO
Date: Thu, 10 Feb 2011 19:32:31 -0000
From: Scott <scott@notabs.org>
X-Patchwork-Id: 2619
Message-Id: <46BB7DA45F6A4D8F85B38E0F7EC230A1@m3a78>
To: <coreboot@coreboot.org>

According to AMD documentation, cache type WP should be used for
execution from flash memory. Coreboot uses WB. While there is no
noticeable performance difference between the two settings, use
of WB can cause a problem for a jtag debugger. The attached
patch changes AMD cache as ram setting for flash execution from
WB to WP.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>


Index: src/cpu/amd/car/cache_as_ram.inc
===================================================================
--- src/cpu/amd/car/cache_as_ram.inc	(revision 6341)
+++ src/cpu/amd/car/cache_as_ram.inc	(working copy)
@@ -294,11 +294,11 @@
 	xorl	%edx, %edx
 	/*
 	 * IMPORTANT: The two lines below can _not_ be written like this:
-	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax
 	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$REAL_XIP_ROM_BASE, %eax
-	orl	$MTRR_TYPE_WRBACK, %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx