From patchwork Thu Feb 17 06:37:33 2011
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Subject: Fam10 FIDVID in SVI 04/25
Date: Thu, 17 Feb 2011 06:37:33 -0000
From: xdrudis <xdrudis@tinet.cat>
X-Patchwork-Id: 2651
Message-Id: <20110217063733.GH8966@ideafix.casa.ct>
To: coreboot@coreboot.org

see patch


Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage 
handling for Fam 10 in SVI mode). 

No change of behaviour intended.

Refactor FAM10 fidvid . prep_fid_change was already long and it'd 
get longer with forthcoming patches. We now take apart F3xDC[NbsynPtrAdj], 
Northbridge/core synchronization FIFO pointer adjust, to its own function. 

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>

--- src/cpu/amd/model_10xxx/fidvid.c	2011-02-16 20:51:55.000000000 +0100
+++ src/cpu/amd/model_10xxx/fidvid.c	2011-02-16 20:51:55.000000000 +0100
@@ -258,6 +258,17 @@ static void config_power_ctrl_misc_reg(d
 	}
 }
 
+            
+static void config_nb_syn_ptr_adj(device_t dev) {
+	/* Note the following settings are additional from the ported
+	 * function setFidVidRegs()
+	 */
+	u32 dword = pci_read_config32(dev, 0xDc);
+	dword |= 0x5 << 12;	/* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */
+	pci_write_config32(dev, 0xdc, dword);
+
+}
+
 static void prep_fid_change(void)
 {
         u32 dword;
@@ -281,13 +292,8 @@ static void prep_fid_change(void)
 		config_clk_power_ctrl_reg0(i);
 
                 config_power_ctrl_misc_reg(dev);
-             
-		/* Note the following settings are additional from the ported
-		 * function setFidVidRegs()
-		 */
-		dword = pci_read_config32(dev, 0xDc);
-		dword |= 0x5 << 12;	/* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */
-		pci_write_config32(dev, 0xdc, dword);
+
+ 		config_nb_syn_ptr_adj(dev);
 
 		/* Rev B settings - FIXME: support other revs. */
 		dword = 0xA0E641E6;