Patchwork Fam10 FIDVID in SVI 06/25

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Submitter xdrudis
Date 2011-02-17 06:38:19
Message ID <20110217063819.GJ8966@ideafix.casa.ct>
Download mbox | patch
Permalink /patch/2653/
State Accepted
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Comments

xdrudis - 2011-02-17 06:38:19
see patch
Marc Jones - 2011-02-27 23:57:42
On Wed, Feb 16, 2011 at 11:38 PM, xdrudis <xdrudis@tinet.cat> wrote:
> see patch
>
Acked-by: Marc Jones <marcj303@gmail.com>

r6392

Patch

Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode). 

No change of behaviour intended.

Refactor FAM10 fidvid. Factor out a little common code. 
Also, our earlier  config_clk_power_ctrl_reg0
was still too long and it'd get longer with forthcoming patches. 
We now take apart F3xD4[PowerStepUp,PowerStepDown]
to its own function. 

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>

--- src/cpu/amd/model_10xxx/fidvid.c	2011-02-16 20:51:55.000000000 +0100
+++ src/cpu/amd/model_10xxx/fidvid.c	2011-02-16 20:51:55.000000000 +0100
@@ -179,32 +179,16 @@  static void recalculateVsSlamTimeSetting
 	pci_write_config32(dev, 0xd8, dtemp);
 }
 
-static void config_clk_power_ctrl_reg0(int node) {         
-        u32 dword;
-      	device_t dev = NODE_PCI(node, 3);
-	/* Program fields in Clock Power/Control register0 (F3xD4) */
-
-	/* set F3xD4 Clock Power/Timing Control 0 Register
-	 * NbClkDidApplyAll=1b
-	 * NbClkDid=100b
-	 * PowerStepUp= "platform dependent"
-	 * PowerStepDown= "platform dependent"
-	 * LinkPllLink=01b
-	 * ClkRampHystSel=HW default
-	 */
+static u32 power_up_down(int node) {
+       u32 dword=0;
 	/* check platform type */
 	if (!(get_platform_type() & AMD_PTYPE_SVR)) {
 		/* For non-server platform
 		 * PowerStepUp=01000b - 50nS
 		 * PowerStepDown=01000b - 50ns
 		 */
-		dword = pci_read_config32(dev, 0xd4);
-		dword &= CPTC0_MASK;
-		dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 | LNK_PLL_LOCK;	/* per BKDG */
-		pci_write_config32(dev, 0xd4, dword);
+        	dword |= PW_STP_UP50 | PW_STP_DN50 ; 
 	} else {
-		dword = pci_read_config32(dev, 0xd4);
-		dword &= CPTC0_MASK;
 		/* get number of cores for PowerStepUp & PowerStepDown in server
 		   1 core - 400nS  - 0000b
 		   2 cores - 200nS - 0010b
@@ -226,9 +210,31 @@  static void config_clk_power_ctrl_reg0(i
 			dword |= PW_STP_UP100 | PW_STP_DN100;
 			break;
 		}
-		dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK;
-		pci_write_config32(dev, 0xd4, dword);
 	}
+        return dword; 
+}
+
+static void config_clk_power_ctrl_reg0(int node) {         
+       	device_t dev = NODE_PCI(node, 3);
+
+
+	/* Program fields in Clock Power/Control register0 (F3xD4) */
+
+	/* set F3xD4 Clock Power/Timing Control 0 Register
+	 * NbClkDidApplyAll=1b
+	 * NbClkDid=100b
+	 * PowerStepUp= "platform dependent"
+	 * PowerStepDown= "platform dependent"
+	 * LinkPllLink=01b
+	 * ClkRampHystSel=HW default
+	 */
+        u32 dword= pci_read_config32(dev, 0xd4);
+	dword &= CPTC0_MASK;
+	dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK;	/* per BKDG */
+        dword |= power_up_down(node);
+
+	pci_write_config32(dev, 0xd4, dword);
+
 }
 
 static void config_power_ctrl_misc_reg(device_t dev) {