Patchwork Fam10 FIDVID in SVI 13/25

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Submitter xdrudis
Date 2011-02-17 06:40:40
Message ID <20110217064040.GQ8966@ideafix.casa.ct>
Download mbox | patch
Permalink /patch/2660/
State Accepted
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Comments

xdrudis - 2011-02-17 06:40:40
see patch
Marc Jones - 2011-02-28 02:35:21
On Wed, Feb 16, 2011 at 11:40 PM, xdrudis <xdrudis@tinet.cat> wrote:
> see patch

Acked-by: Marc Jones <marcj303@gmail.com>

r6399

Patch

Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode. 

Contemplate the possibility of nbCofVidUpdate not being 
defined, trying to get closer to BKDG 

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>

--- src/cpu/amd/model_10xxx/fidvid.c	2011-02-13 21:09:15.000000000 +0100
+++ src/cpu/amd/model_10xxx/fidvid.c	2011-02-13 21:12:48.000000000 +0100
@@ -631,7 +631,11 @@ 
 	nodes = get_nodes();
 	nb_cof_vid_update = 0;
 	for (i = 0; i < nodes; i++) {
-		if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) {
+                u32 cpuRev = mctGetLogicalCPUID(i) ;
+                u32 nbCofVidUpdateDefined = (cpuRev & (AMD_FAM10_LT_D));
+		if (nbCofVidUpdateDefined 
+                    && (pci_read_config32(NODE_PCI(i, 3), 0x1FC) 
+                        & NB_COF_VID_UPDATE_MASK)) {
 			nb_cof_vid_update = 1;
 			break;
 		}
--- src/northbridge/amd/amdht/AsPsDefs.h	2011-02-13 21:09:20.000000000 +0100
+++ src/northbridge/amd/amdht/AsPsDefs.h	2011-02-13 21:15:16.000000000 +0100
@@ -229,6 +229,8 @@ 
 /* F3x1F0 Product Information Register */
 #define NB_PSTATE_MASK 0x00070000 /* NbPstate for CPU rev C3 */
 
+/* F3x1FC Product Information Register */
+#define NB_COF_VID_UPDATE_MASK 1 /* for CPU rev <= C */
 
 #define NM_PS_REG 5			/* number of P-state MSR registers */
 

--- src/northbridge/amd/amdmct/amddefs.h	2011-02-13 21:09:21.000000000 +0100
+++ src/northbridge/amd/amdmct/amddefs.h	2011-02-13 21:20:44.000000000 +0100
@@ -63,6 +63,7 @@ 
 #define	AMD_DR_GT_B0	(AMD_DR_ALL & ~(AMD_DR_B0))
 #define	AMD_DR_ALL	(AMD_DR_Bx)
 #define	AMD_FAM10_ALL	(AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 )
+#define AMD_FAM10_LT_D  (AMD_FAM10_ALL & ~(AMD_HY_D0))
 #define	AMD_FAM10_GT_B0	(AMD_FAM10_ALL & ~(AMD_DR_B0))
 #define	AMD_DA_Cx       (AMD_DA_C2 | AMD_DA_C3)
 #define	AMD_DR_Cx       (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx)