Patchwork Fam10 FIDVID in SVI 15/25

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Submitter xdrudis
Date 2011-02-17 06:43:15
Message ID <20110217064315.GS8966@ideafix.casa.ct>
Download mbox | patch
Permalink /patch/2662/
State Accepted
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Comments

xdrudis - 2011-02-17 06:43:15
see patch
Marc Jones - 2011-02-28 03:08:33
On Wed, Feb 16, 2011 at 11:43 PM, xdrudis <xdrudis@tinet.cat> wrote:
> see patch
>
Acked-by: Marc Jones <marcj303@gmail.com>

r6402

Patch

Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode. 

Looking at BKDG the process for updating 
Pstate Nb vid after warn reset seemed 
more similar to the codethat was there fo
pvi than the one for svi, so I called the
pvi function passing a pvi/svi flag. I don't
find documentation on why should UpdateSinglePlaneNbVid()
be called in PVI, but since I can't test it, 
I leave it as it was. 

This patch showed some progress beyond fidvid in my
boar,d but only sometimes, most times it just didn't 
work.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>

--- src/cpu/amd/model_10xxx/fidvid.c	2011-02-13 23:08:32.000000000 +0100
+++ src/cpu/amd/model_10xxx/fidvid.c	2011-02-14 01:10:08.000000000 +0100
@@ -732,36 +732,17 @@ 
 
 }
 
-static void updateSviPsNbVidAfterWR(u32 newNbVid)
-{
-	msr_t msr;
-	u8 i;
-
-	/* This function copies newNbVid to NbVid bits in P-state Registers[4:0]
-	 * for SVI mode.
-	 */
-
-	for (i = 0; i < 5; i++) {
-		msr = rdmsr(0xC0010064 + i);
-		if ((msr.hi >> 31) & 1) {	/* PstateEn? */
-			msr.lo &= ~(0x7F << 25);
-			msr.lo |= (newNbVid & 0x7F) << 25;
-			wrmsr(0xC0010064 + i, msr);
-		}
-	}
-}
-
-
-static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll)
+static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) 
 {
 	msr_t msr;
 	u8 i;
 	u8 StartupPstate;
 
-	/* This function copies newNbVid to NbVid bits in P-state
-	 * Registers[4:0] if its NbDid bit=0 and PstateEn bit =1 in case of
-	 * NbVidUpdatedAll =0 or copies copies newNbVid to NbVid bits in
-	 * P-state Registers[4:0] if its and PstateEn bit =1 in case of
+	/* BKDG 2.4.2.9.1 11-12
+         * This function copies newNbVid to NbVid bits in P-state
+	 * Registers[4:0] if its NbDid bit=0, and IddValue!=0 in case of
+	 * NbVidUpdatedAll =0 or copies newNbVid to NbVid bits in
+	 * P-state Registers[4:0] if its IddValue!=0 in case of
 	 * NbVidUpdatedAll=1. Then transition to StartPstate.
 	 */
 
@@ -769,26 +750,28 @@ 
 	for (i = 0; i < 5; i++) {
 		msr = rdmsr(0xC0010064 + i);
 		/*  NbDid (bit 22 of P-state Reg) == 0  or NbVidUpdatedAll = 1 */
-		if ((((msr.lo >> 22) & 1) == 0) || NbVidUpdatedAll) {
-			msr.lo &= ~(0x7F << 25);
-			msr.lo |= (newNbVid & 0x7F) << 25;
+		if (   (msr.hi & PS_IDD_VALUE_MASK) 
+                    && (msr.hi & PS_EN_MASK)
+                    &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) {
+			msr.lo &= PS_NB_VID_M_OFF;
+			msr.lo |= (newNbVid & 0x7F) << PS_NB_VID_SHFT;
 			wrmsr(0xC0010064 + i, msr);
 		}
 	}
 
-	UpdateSinglePlaneNbVid();
-
+        /* Not documented. Would overwrite Nb_Vids just copied
+         * should we just update cpu_vid or nothing at all ?
+	 */
+	if (pviMode) { //single plane
+            UpdateSinglePlaneNbVid();
+	}
 	/* For each core in the system, transition all cores to StartupPstate */
 	msr = rdmsr(0xC0010071);
 	StartupPstate = msr.hi & 0x07;
-	msr = rdmsr(0xC0010062);
-	msr.lo = StartupPstate;
-	wrmsr(0xC0010062, msr);
-
-	/* Wait for StartupPstate to set. */
-	do {
-		msr = rdmsr(0xC0010063);
-	} while (msr.lo != StartupPstate);
+       
+	/* Set and wait for StartupPstate to set. */
+        set_pstate(StartupPstate);
+
 }
 
 static void finalPstateChange(void)
@@ -823,15 +806,12 @@ 
 	NbVidUpdateAll = (reg1fc >> 1) & 1;
 
 	if (nb_cof_vid_update) {
-		if (pvimode) {
-			nbvid = (reg1fc >> 7) & 0x7F;
-			/* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
-			fixPsNbVidAfterWR(nbvid, NbVidUpdateAll);
-		} else {	/* SVI */
-			nbvid = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F);
-			updateSviPsNbVidAfterWR(nbvid);
+		if (!pvimode) {	/* SVI */
+			nbvid = nbvid - ((reg1fc >> 17) & 0x1F);
 		}
-	} else {		/* !nb_cof_vid_update */
+		/* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
+		fixPsNbVidAfterWR(nbvid, NbVidUpdateAll,pvimode);
+ 	} else {		/* !nb_cof_vid_update */
 		if (pvimode)
 			UpdateSinglePlaneNbVid();
 	}
--- src/northbridge/amd/amdht/AsPsDefs.h	2011-02-13 22:19:01.000000000 +0100
+++ src/northbridge/amd/amdht/AsPsDefs.h	2011-02-14 01:10:13.000000000 +0100
@@ -44,6 +44,10 @@ 
 #define PS_REG3 3			/* offset for P3 */
 #define PS_REG4 4			/* offset for P4 */
 
+#define PS_IDD_VALUE_SHFT 0            /* IddValue: current value
+					  field offset for msr.hi */
+#define PS_IDD_VALUE_MASK 0xFF         /* IddValue: current value
+					  field mask for msr.hi */
 #define PS_PSDIS_MASK	0x7fffffff	/* disable P-state register */
 #define PS_EN_MASK  0x80000000		/* P-state register enable mask */
 #define PS_NB_DID_MASK 0x400000	/* P-state Reg[NbDid] Mask */