Fam10 FIDVID in SVI 16/25

Submitter	xdrudis
Date	2011-02-17 06:43:31
Message ID	<20110217064331.GT8966@ideafix.casa.ct>
Download	mbox \| patch
Permalink	/patch/2663/
State	Accepted
Headers	show Return-path: <coreboot-bounces@coreboot.org> Envelope-to: patchwork@coreboot.org Date: Thu, 17 Feb 2011 07:43:31 +0100 To: coreboot@coreboot.org Message-ID: <20110217064331.GT8966@ideafix.casa.ct> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="K8zN2sh9fO5jmbe4" Content-Disposition: inline In-Reply-To: <35042.1297863902@tinet.org> User-Agent: Mutt/1.5.20 (2009-06-14) From: xdrudis <xdrudis@tinet.cat> Subject: [coreboot] [PATCH] Fam10 FIDVID in SVI 16/25 Precedence: list Errors-To: coreboot-bounces@coreboot.org Sender: coreboot-bounces@coreboot.org

Comments

xdrudis - 2011-02-17 06:43:31

see patch

Marc Jones - 2011-02-28 03:12:24

On Wed, Feb 16, 2011 at 11:43 PM, xdrudis <xdrudis@tinet.cat> wrote:
> see patch
>

Acked-by: Marc Jones <marcj303@gmail.com>

r6403

Patch

Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode. 

Add to init_fidvid_stage2 some step for my CPU (rev C3) 
mentioned in BKDG 2.4.2.6 (5) that was missing  
 
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>


--- src/cpu/amd/model_10xxx/fidvid.c	2011-02-14 01:10:08.000000000 +0100
+++ src/cpu/amd/model_10xxx/fidvid.c	2011-02-14 23:11:05.000000000 +0100
@@ -65,6 +65,25 @@ 
 		       dword);
 	}
 }
+static void enableNbPState1( device_t dev ) {
+  u32 cpuRev =  mctGetLogicalCPUID(0xFF);
+  if (cpuRev & AMD_FAM10_C3) {
+    u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK);
+    if ( nbPState){
+      u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT;
+      u32 i;
+      for (i = nbPState; i < NM_PS_REG; i++) {
+         msr_t msr =  rdmsr(PS_REG_BASE + i);
+         if (msr.hi &  PS_EN_MASK ) {
+            msr.hi |= NB_DID_M_ON;
+            msr.lo &= NB_VID_MASK_OFF;
+	    msr.lo |= ( nbVid1 << NB_VID_POS);
+	    wrmsr(PS_REG_BASE + i, msr);
+	 }
+      }
+    }
+  }
+}
 
 static void setVSRamp(device_t dev) {
 	/* BKDG r31116 2010-04-22  2.4.1.7 step b F3xD8[VSRampTime] 
@@ -820,6 +839,7 @@ 
 	dtemp |= PLLLOCK_DFT_L;
 	pci_write_config32(dev, 0xA0, dtemp);
 
+        enableNbPState1(dev);
 	finalPstateChange();
 
 	/* Set TSC to tick at the P0 ndfid rate */
--- src/northbridge/amd/amdht/AsPsDefs.h	2011-02-14 01:10:13.000000000 +0100
+++ src/northbridge/amd/amdht/AsPsDefs.h	2011-02-14 23:11:11.000000000 +0100
@@ -153,6 +153,8 @@ 
 #define PS_2 0x00020000		/* P-state 2 */
 #define PS_CPU_DID_1 0x40		/* Cpu Did 1 */
 
+#define NB_VID1_MASK  0x00003f80      /* F3x1F4[NbVid1]*/
+#define NB_VID1_SHIFT  7      /* F3x1F4[NbVid1] */

Patchwork Fam10 FIDVID in SVI 16/25

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Patch