Comments
Patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
I don't understand what this was doing nor find docs for these regs
Maybe it was left over from some copy & paste ?
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
@@ -394,19 +394,6 @@
} else { /* SVI */
/* set slamVidMode to 1 for SVI */
dword |= VID_SLAM_ON;
-
- u32 dtemp = dword;
-
- /* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd] */
- dword = pci_read_config32(dev, 0xD8);
-
- if (dtemp & DUAL_VDD_BIT)
- dword |= PWR_PLN_ON;
- else
- dword &= PWR_PLN_OFF;
- pci_write_config32(dev, 0xD8, dword);
-
- dword = dtemp;
}
/* set the rest of A0 since we're at it... */