From patchwork Thu Feb 17 06:45:59 2011
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Subject: Fam10 FIDVID in SVI 23/25
Date: Thu, 17 Feb 2011 06:45:59 -0000
From: xdrudis <xdrudis@tinet.cat>
X-Patchwork-Id: 2670
Message-Id: <20110217064559.GA8966@ideafix.casa.ct>
To: coreboot@coreboot.org

see patch
Acked-by: Marc Jones <marcj303@gmail.com>


Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode. 

I remove an unused parameter and a duplicated constant. 
 
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>

--- src/cpu/amd/model_10xxx/fidvid.c	2011-02-16 01:08:16.000000000 +0100
+++ src/cpu/amd/model_10xxx/fidvid.c	2011-02-16 09:20:39.000000000 +0100
@@ -772,7 +772,7 @@
 
 }
 
-static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid)
+static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid)
 {
 	u32 send;
 
--- src/cpu/amd/model_10xxx/init_cpus.c	2011-02-16 01:08:16.000000000 +0100
+++ src/cpu/amd/model_10xxx/init_cpus.c	2011-02-16 09:20:39.000000000 +0100
@@ -157,7 +157,7 @@
 }
 
 #if CONFIG_SET_FIDVID
-static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid);
+static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
 #endif
 
 static inline __attribute__ ((always_inline))
@@ -344,8 +344,7 @@
 				printk(BIOS_DEBUG,
 				       "init_fidvid_ap(stage1) apicid: %02x\n",
 				       apicid);
-				init_fidvid_ap(bsp_apicid, apicid, id.nodeid,
-					       id.coreid);
+				init_fidvid_ap(apicid, id.nodeid, id.coreid);
 			}
 		}
 #endif
--- src/northbridge/amd/amdht/AsPsDefs.h	2011-02-16 01:08:22.000000000 +0100
+++ src/northbridge/amd/amdht/AsPsDefs.h	2011-02-16 09:20:44.000000000 +0100
@@ -58,7 +58,6 @@
 #define PS_NB_VID_SHFT 25		/* P-state bit shift for NbVid */
 #define PS_BOTH_VID_OFF 0x01ff01ff	/* Mask NbVid & CpuVid */
 #define PS_CPU_NB_VID_SHFT 16		/* P-state bit shift from CpuVid to NbVid */
-#define PS_NB_VID_SHFT 25		/* P-state NBVID shift */
 #define PS_DIS 0x7fffffff		/* disable P-state reg */
 #define PS_EN 0x80000000		/* enable P-state reg */
 #define PS_CPU_FID_MASK 0x03f           /* MSRC001_00[68:64][CpuFid]