Patchwork Coreboot for AMD Fusion family 14h: ASRock E350M1

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Submitter Scott
Date 2011-02-24 04:03:32
Message ID <932253EDC06E47FFB727A3FDCEAE6D8A@m3a78>
Download mbox | patch
Permalink /patch/2687/
State Superseded
Headers show

Comments

Scott - 2011-02-24 04:03:32
The attached patch gets coreboot going on the ASRock E350M1 board.
This is an AMD family 14h Fusion board I bought for US $120, including
processor. The video option rom is from the supplied UEFI BIOS.

The patch modifies the persimmon project and is for development use,
not for commit. With this patch it can boot DOS from a SATA drive.
It can also boot WinPE from a USB flash drive. I was unable to get
Windows setup to run.

The board has a socketed SPI flash BIOS chip and a serial port
header. The SIO is Nuvoton NCT5572D. Using coreboot's existing
Winbond w83627hf is a good enough match to at least get the serial
port and keyboard going.

Here are pictures of the board:
http://notabs.org/pictures/ASRock-E350M1/


Thanks,
Scott
Peter Stuge - 2011-02-24 04:14:30
Scott Duplichan wrote:
> The attached patch gets coreboot going on the ASRock E350M1 board.
> This is an AMD family 14h Fusion board I bought for US $120, including
> processor. The video option rom is from the supplied UEFI BIOS.
> 
> The patch modifies the persimmon project and is for development use,
> not for commit.

What would you like to add functionally before commiting?


//Peter
Scott - 2011-02-24 04:25:01
-----Original Message-----
From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Peter Stuge
Sent: Wednesday, February 23, 2011 10:15 PM
To: coreboot@coreboot.org
Subject: Re: [coreboot] Coreboot for AMD Fusion family 14h: ASRock E350M1

Scott Duplichan wrote:
> The attached patch gets coreboot going on the ASRock E350M1 board.
> This is an AMD family 14h Fusion board I bought for US $120, including
> processor. The video option rom is from the supplied UEFI BIOS.
> 
> The patch modifies the persimmon project and is for development use,
> not for commit.

]What would you like to add functionally before commiting?

I guess the main thing to do before a commit is to branch persimmon
and make an asrock e350m1 project. I suspect the functionality, while
not ideal, is similar to that of persimmon. I will try to make a
proper patch...
Thanks,
Scott


//Peter
Peter Stuge - 2011-02-24 04:34:53
Scott Duplichan wrote:
> > The patch modifies the persimmon project and is for development
> > use, not for commit.
> 
> ]What would you like to add functionally before commiting?
> 
> I guess the main thing to do before a commit is to branch persimmon
> and make an asrock e350m1 project. I suspect the functionality,
> while not ideal, is similar to that of persimmon. I will try to
> make a proper patch...

Great! Use svn cp to create the directory, then put your changes in
there, and then svn diff should create the corresponding small patch
that you sent already. I'm happy to ack. This looks like a nice board
for a media center system.


//Peter
Paul Menzel - 2011-02-24 12:37:27
Am Donnerstag, den 24.02.2011, 05:34 +0100 schrieb Peter Stuge:
> Scott Duplichan wrote:

These are really great news.

[…]

> This looks like a nice board for a media center system.

Indeed. There are some reviews available of this board [1][2].

Unfortunately in Germany all the online shops seem to be out of stock
[3]. The board would cost around 90 €.


Thanks,

Paul


[1] http://www.fudzilla.com/reviews/item/21897-asrock-e350m1-brazos-review/21897-asrock-e350m1-brazos-review?start=4
[2] http://www.tomshardware.com/reviews/asrock-e350m1-amd-brazos-zacate-apu,2840-14.html
[3] http://www.preistrend.de/Preisvergleich_ASRock_E350M1__x7249770B04777704.html
Stefan Reinauer - 2011-02-24 21:26:06
* Scott Duplichan <scott@notabs.org> [110224 05:03]:
> The attached patch gets coreboot going on the ASRock E350M1 board.
> This is an AMD family 14h Fusion board I bought for US $120, including
> processor. The video option rom is from the supplied UEFI BIOS.
> 
> The patch modifies the persimmon project and is for development use,
> not for commit. With this patch it can boot DOS from a SATA drive.
> It can also boot WinPE from a USB flash drive. I was unable to get
> Windows setup to run.
> 
> The board has a socketed SPI flash BIOS chip and a serial port
> header. The SIO is Nuvoton NCT5572D. Using coreboot's existing
> Winbond w83627hf is a good enough match to at least get the serial
> port and keyboard going.
> 
> Here are pictures of the board:
> http://notabs.org/pictures/ASRock-E350M1/
 

> +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)                                                                                                                                                                                                 
if CONFIG_SIO_PORT is defined in Kconfig (why?) we could as well use it
in romstage.c. Is there a chance to remove it from Kconfig instead?
Scott - 2011-02-25 01:02:27
Stefan Reinauer wrote: 

]> +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

]if CONFIG_SIO_PORT is defined in Kconfig (why?) we could as well use it
]in romstage.c. Is there a chance to remove it from Kconfig instead?

Certainly the two occurrences of 2e is not ideal. This change works:

-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1)

I believe most SIOs have a strap option for 4e, so presumably this
address needs to be project selectable by some method. Phoenix
legacy BIOS actually figures it out at runtime. That method seems
dangerous to me and makes stepping through the code tedious.

If we remove it from kconfig, would it just be local to romstage.c?
I suppose this would be a separate patch, given the number of projects
affected.

Thanks,
Scott
Stefan Reinauer - 2011-02-25 19:31:52
* Scott Duplichan <scott@notabs.org> [110225 02:02]:
> Stefan Reinauer wrote: 
> 
> ]> +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
> 
> ]if CONFIG_SIO_PORT is defined in Kconfig (why?) we could as well use it
> ]in romstage.c. Is there a chance to remove it from Kconfig instead?
> 
> Certainly the two occurrences of 2e is not ideal. This change works:
> 
> -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
> +#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1)
 
That would work. Or leave the first version and we try to get rid of the
Kconfig variable later on...

Anyways
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

> I believe most SIOs have a strap option for 4e, so presumably this
> address needs to be project selectable by some method. Phoenix
> legacy BIOS actually figures it out at runtime. That method seems
> dangerous to me and makes stepping through the code tedious.

You can certainly detect where it lives and what kind of device it is
(though I have not seen Phoenix do that during runtime on intel systems,
according to SerialICE) .. The one thing I think you can not probe is
how the ports are wired up (i.e. if you have two Super I/O chips, is the
one serial port connected to the first or second chip)

> If we remove it from kconfig, would it just be local to romstage.c?
> I suppose this would be a separate patch, given the number of projects
> affected.

There's always at least another occurence in devicetree.cb. But that is
not used in romstage, only in ramstage.

Maybe it is time to think about extending the devicetree.cb so it can be
used by romstage, too? But that's for another mail.

Patch

Index: src/mainboard/amd/persimmon/BiosCallOuts.c
===================================================================
--- src/mainboard/amd/persimmon/BiosCallOuts.c	(revision 6375)
+++ src/mainboard/amd/persimmon/BiosCallOuts.c	(working copy)
@@ -432,6 +432,12 @@ 
 /*  Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
+  MEM_DATA_STRUCT *MemData = ConfigPtr;
+
+  // skipping memclr is a good way to reduce boot time on non-ecc systems.
+  // But this fails, suggesting either agesa or coreboot is incorrectly
+  // relying in cleared memory.
+  // MemData->ParameterListPtr->EnableMemClr = FALSE;
   return AGESA_SUCCESS;
 }
 /*  Call the host environment interface to provide a user hook opportunity. */
Index: src/mainboard/amd/persimmon/devicetree.cb
===================================================================
--- src/mainboard/amd/persimmon/devicetree.cb	(revision 6375)
+++ src/mainboard/amd/persimmon/devicetree.cb	(working copy)
@@ -55,30 +55,46 @@ 
                                         device pci 14.1 on end # IDE    0x439c
                                         device pci 14.2 on end # HDA    0x4383
                                         device pci 14.3 on # LPC        0x439d
-					        chip superio/fintek/f81865f
-							device pnp 4e.0 off		# Floppy
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
 								io 0x60 = 0x3f0
 								irq 0x70 = 6
 								drq 0x74 = 2
 							end
-							device pnp 4e.3 off end			# Parallel Port
-							device pnp 4e.4 off end			# Hardware Monitor
-							device pnp 4e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
+							device pnp 2e.1 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
 							end
-							device pnp 4e.6 off end			# GPIO
-							device pnp 4e.a off end			# PME
-							device pnp 4e.10 on			# COM1
+							device pnp 2e.2 on #  Com1
 								io 0x60 = 0x3f8
 								irq 0x70 = 4
 							end
-							device pnp 4e.11 off			# COM2
+							device pnp 2e.3 off #  Com2
 								io 0x60 = 0x2f8
 								irq 0x70 = 3
 							end
-                                                end # f81865f
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+								irq 0x72 = 12
+							end
+							device pnp 2e.6 off #  CIR
+								io 0x60 = 0x100
+							end
+							device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.8 off end #  GPIO2
+							device pnp 2e.9 off end #  GPIO3
+							device pnp 2e.a off end #  ACPI
+							device pnp 2e.b on #  HW Monitor
+								io 0x60 = 0x290
+								irq 0x70 = 5
+							end
+						end
 					end #LPC
   					device pci 14.4 on end # PCI 0x4384
 	  				device pci 14.5 on end # USB 2
Index: src/mainboard/amd/persimmon/dimmSpd.c
===================================================================
--- src/mainboard/amd/persimmon/dimmSpd.c	(revision 6375)
+++ src/mainboard/amd/persimmon/dimmSpd.c	(working copy)
@@ -34,8 +34,8 @@ 
    {
    // socket 0
       {
-         {0xA0, 0xA2},  // channel 0 dimms
-         {0xA4, 0xA8},  // channel 1 dimms
+         {0xA0, 0xA4},  // channel 0 dimms
+         {0x00, 0x00},  // channel 1 dimms
       },
    // socket 1
       {
Index: src/mainboard/amd/persimmon/Kconfig
===================================================================
--- src/mainboard/amd/persimmon/Kconfig	(revision 6375)
+++ src/mainboard/amd/persimmon/Kconfig	(working copy)
@@ -28,7 +28,7 @@ 
   select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
   select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
   select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
-	select SUPERIO_FINTEK_F81865F
+	select SUPERIO_WINBOND_W83627HF
   select BOARD_HAS_FADT
         select HAVE_BUS_CONFIG
         select HAVE_OPTION_TABLE
@@ -41,7 +41,7 @@ 
   select SERIAL_CPU_INIT
   select AMDMCT
         select HAVE_ACPI_TABLES
-  select BOARD_ROMSIZE_KB_4096
+  select BOARD_ROMSIZE_KB_1024
   select ENABLE_APIC_EXT_ID
   select TINY_BOOTBLOCK
         select GFXUMA
@@ -132,16 +132,16 @@ 
 
 config SIO_PORT
         hex
-        default 0x4e
+        default 0x2e
 
 config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-#define CONFIG_VGA_BIOS_ID "1002,9804"
+#define CONFIG_VGA_BIOS_ID "1002,9802"
 config VGA_BIOS_ID
         string
-        default "1002,9804"
+        default "1002,9802"
 
 config DRIVERS_PS2_KEYBOARD
 	bool
@@ -151,5 +151,27 @@ 
 	bool
 	default n
 
+# ----------------overrides--------------------
+
+config DEFAULT_CONSOLE_LOGLEVEL
+	default 4
+
+config VGA_BIOS
+   default y
+
+config VGA_BIOS_FILE
+	default "../optionroms/asrock-vga.bin"
+
+config PAYLOAD_FILE
+	default "../seabios-for-coreboot/out/bios.bin.elf"
+
+config DRIVERS_PS2_KEYBOARD
+	default n
+
+config VGA_ROM_RUN
+	default n
+
+config PCI_ROM_RUN
+	default n
 endif # BOARD_AMD_PERSIMMON
 
Index: src/mainboard/amd/persimmon/romstage.c
===================================================================
--- src/mainboard/amd/persimmon/romstage.c	(revision 6375)
+++ src/mainboard/amd/persimmon/romstage.c	(working copy)
@@ -31,16 +31,16 @@ 
 #include <console/loglevel.h>
 #include "agesawrapper.h"
 #include "cpu/x86/bist.h"
-#include "superio/fintek/f81865f/f81865f_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "pc80/i8254.c"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #include "pc80/i8259.c"
 #include "SbEarly.h"
 #include "SBPLATFORM.h"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -52,7 +52,7 @@ 
     sb_poweron_init();
 
     post_code(0x31);
-    f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
     uart_init();
     console_init();
   }