From patchwork Thu Feb 24 04:03:32 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Coreboot for AMD Fusion family 14h: ASRock E350M1 Date: Thu, 24 Feb 2011 04:03:32 -0000 From: Scott X-Patchwork-Id: 2687 Message-Id: <932253EDC06E47FFB727A3FDCEAE6D8A@m3a78> To: The attached patch gets coreboot going on the ASRock E350M1 board. This is an AMD family 14h Fusion board I bought for US $120, including processor. The video option rom is from the supplied UEFI BIOS. The patch modifies the persimmon project and is for development use, not for commit. With this patch it can boot DOS from a SATA drive. It can also boot WinPE from a USB flash drive. I was unable to get Windows setup to run. The board has a socketed SPI flash BIOS chip and a serial port header. The SIO is Nuvoton NCT5572D. Using coreboot's existing Winbond w83627hf is a good enough match to at least get the serial port and keyboard going. Here are pictures of the board: http://notabs.org/pictures/ASRock-E350M1/ Thanks, Scott Acked-by: Stefan Reinauer Index: src/mainboard/amd/persimmon/BiosCallOuts.c =================================================================== --- src/mainboard/amd/persimmon/BiosCallOuts.c (revision 6375) +++ src/mainboard/amd/persimmon/BiosCallOuts.c (working copy) @@ -432,6 +432,12 @@ /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { + MEM_DATA_STRUCT *MemData = ConfigPtr; + + // skipping memclr is a good way to reduce boot time on non-ecc systems. + // But this fails, suggesting either agesa or coreboot is incorrectly + // relying in cleared memory. + // MemData->ParameterListPtr->EnableMemClr = FALSE; return AGESA_SUCCESS; } /* Call the host environment interface to provide a user hook opportunity. */ Index: src/mainboard/amd/persimmon/devicetree.cb =================================================================== --- src/mainboard/amd/persimmon/devicetree.cb (revision 6375) +++ src/mainboard/amd/persimmon/devicetree.cb (working copy) @@ -55,30 +55,46 @@ device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 + device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.11 off # COM2 + device pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - end # f81865f + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 Index: src/mainboard/amd/persimmon/dimmSpd.c =================================================================== --- src/mainboard/amd/persimmon/dimmSpd.c (revision 6375) +++ src/mainboard/amd/persimmon/dimmSpd.c (working copy) @@ -34,8 +34,8 @@ { // socket 0 { - {0xA0, 0xA2}, // channel 0 dimms - {0xA4, 0xA8}, // channel 1 dimms + {0xA0, 0xA4}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms }, // socket 1 { Index: src/mainboard/amd/persimmon/Kconfig =================================================================== --- src/mainboard/amd/persimmon/Kconfig (revision 6375) +++ src/mainboard/amd/persimmon/Kconfig (working copy) @@ -28,7 +28,7 @@ select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 - select SUPERIO_FINTEK_F81865F + select SUPERIO_WINBOND_W83627HF select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE @@ -41,7 +41,7 @@ select SERIAL_CPU_INIT select AMDMCT select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 + select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID select TINY_BOOTBLOCK select GFXUMA @@ -132,16 +132,16 @@ config SIO_PORT hex - default 0x4e + default 0x2e config ONBOARD_VGA_IS_PRIMARY bool default y -#define CONFIG_VGA_BIOS_ID "1002,9804" +#define CONFIG_VGA_BIOS_ID "1002,9802" config VGA_BIOS_ID string - default "1002,9804" + default "1002,9802" config DRIVERS_PS2_KEYBOARD bool @@ -151,5 +151,27 @@ bool default n +# ----------------overrides-------------------- + +config DEFAULT_CONSOLE_LOGLEVEL + default 4 + +config VGA_BIOS + default y + +config VGA_BIOS_FILE + default "../optionroms/asrock-vga.bin" + +config PAYLOAD_FILE + default "../seabios-for-coreboot/out/bios.bin.elf" + +config DRIVERS_PS2_KEYBOARD + default n + +config VGA_ROM_RUN + default n + +config PCI_ROM_RUN + default n endif # BOARD_AMD_PERSIMMON Index: src/mainboard/amd/persimmon/romstage.c =================================================================== --- src/mainboard/amd/persimmon/romstage.c (revision 6375) +++ src/mainboard/amd/persimmon/romstage.c (working copy) @@ -31,16 +31,16 @@ #include #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include "superio/winbond/w83627hf/early_serial.c" #include "cpu/x86/lapic/boot_cpu.c" #include "pc80/i8254.c" +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "pc80/i8259.c" #include "SbEarly.h" #include "SBPLATFORM.h" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -52,7 +52,7 @@ sb_poweron_init(); post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); }