Patchwork 870 attempt

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Submitter Jonathan A. Kollasch
Date 2011-02-24 14:23:20
Message ID <20110224142320.GB5415@tarantulon.kollasch.net>
Download mbox | patch
Permalink /patch/2690/
State Accepted
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Comments

Jonathan A. Kollasch - 2011-02-24 14:23:20
On Thu, Feb 24, 2011 at 02:14:07AM +0000, Jonathan A. Kollasch wrote:
> Hi,
> 
> I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850
> board.  Raminit seems to go okay, as does the first bits of ramstage.
> However, ramstage fails after the first two passes through
> rs780_enable().  It stalls in get_vid_did() reading PCI config space
> of device 2 (or 4).  Also, the rs780 HT init code thinks the link should
> run at 200MHz, maybe that's related.

Attached is the diff, and console output there from.
(Mainboard directory is a svn cp of bimini_fam10.)

	Jonathan Kollasch

coreboot-4.0-r6375:6378M- Thu Feb 24 08:03:37 CST 2011 starting...

BSP Family_Model: 00100f43 
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00 
cpu_init_detectedx = 00000000 
microcode: equivalent rev id  = 0x1043, current patch id = 0x00000000
microcode: patch id to apply = 0x010000b6
microcode: updated to patch id = 0x010000b6  success

cpuSetAMDMSR  done
Enter amd_ht_init()
AMD_CB_EventNotify()
 event class: 02
 event: 2005
 data:  05  00  00  00  01 
AMD_CB_EventNotify()
 event class: 05
 event: 2006
 data:  04  00  00  ff 
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00 
  F3x80: e600a681 
  F3x84: a0e641e6 
  F3xD4: c8810f24 
  F3xD8: 03001716 
  F3xDC: 00005336 
core0 started: 
start_other_cores()
init node: 00  cores: 03 
Start other core - nodeid: 00  cores: 03
started ap apicid:    cccoororerexe:xx ::     ------- --{  {{   AAAPPPIIICICCDIIDD   ===   01002 3 N ONNOODDDEEEIIDID D = = =0  00000  C COCORORERIEEDII DD=  ==   00102}3} }-  --------


* mAimmPcii cc0rrr1ooosccctoooadddreeet::e : de e
qeq
uq*iuu viiAavvPlaa ellnee0tnn2 ttsr  trraeeervt vvi  ediid dd
  
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 ttp  rpspaa7at8tct0chc_h he i aidird d = l =y=0 _ x0s00xex0t000u000p00(000)000000
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ddt
  ttoCoo P aU ap apppRplpeylvl y y= i  =s=0   0K0xx8x0_01011010000000.000
0b0
b6bf66a


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dee
 ddt  rsttooo 7  p8pa0pat_atcpthocc rhhi_  iiidndd i  =t== 
  0
00xxx000101100000000000b6bb6 6   s s bsus8cu0ucc0cec_ceeessasssrs
l

y
Marc Jones - 2011-02-24 16:45:05
On Thu, Feb 24, 2011 at 7:23 AM, Jonathan A. Kollasch
<jakllsch@kollasch.net> wrote:
> On Thu, Feb 24, 2011 at 02:14:07AM +0000, Jonathan A. Kollasch wrote:
>> Hi,
>>
>> I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850
>> board.  Raminit seems to go okay, as does the first bits of ramstage.
>> However, ramstage fails after the first two passes through
>> rs780_enable().  It stalls in get_vid_did() reading PCI config space
>> of device 2 (or 4).  Also, the rs780 HT init code thinks the link should
>> run at 200MHz, maybe that's related.
>
> Attached is the diff, and console output there from.
> (Mainboard directory is a svn cp of bimini_fam10.)
>

>rs780_htinit cpu_ht_freq=0.
>rs780_htinit: HT1 mode

It looks it had problems getting the HT frequency from the CPU. Both
sides have to agree on what is capable. You may need to look at the
CPU HT code for a hint on why it reports what it does to the SB.

Marc
Scott - 2011-02-24 17:07:04
-----Original Message-----
From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Marc Jones
Sent: Thursday, February 24, 2011 10:45 AM
To: Jonathan A. Kollasch
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] 870 attempt

On Thu, Feb 24, 2011 at 7:23 AM, Jonathan A. Kollasch
<jakllsch@kollasch.net> wrote:
> On Thu, Feb 24, 2011 at 02:14:07AM +0000, Jonathan A. Kollasch wrote:
>> Hi,
>>
>> I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850
>> board.  Raminit seems to go okay, as does the first bits of ramstage.
>> However, ramstage fails after the first two passes through
>> rs780_enable().  It stalls in get_vid_did() reading PCI config space
>> of device 2 (or 4).  Also, the rs780 HT init code thinks the link should
>> run at 200MHz, maybe that's related.
>
> Attached is the diff, and console output there from.
> (Mainboard directory is a svn cp of bimini_fam10.)
>

>rs780_htinit cpu_ht_freq=0.
>rs780_htinit: HT1 mode

]It looks it had problems getting the HT frequency from the CPU. Both
]sides have to agree on what is capable. You may need to look at the
]CPU HT code for a hint on why it reports what it does to the SB.
]
]Marc

Also remember that the family 10h swap list problem still exists.
There are some old patches and discussion that might be useful.
Here is an example:

http://www.mail-archive.com/coreboot@coreboot.org/msg27356.html
Jonathan A. Kollasch - 2011-02-24 17:53:30
On Thu, Feb 24, 2011 at 11:07:04AM -0600, Scott Duplichan wrote:
> -----Original Message-----
> From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Marc Jones
> Sent: Thursday, February 24, 2011 10:45 AM
> To: Jonathan A. Kollasch
> Cc: coreboot@coreboot.org
> Subject: Re: [coreboot] 870 attempt
> 
> On Thu, Feb 24, 2011 at 7:23 AM, Jonathan A. Kollasch
> <jakllsch@kollasch.net> wrote:
> > On Thu, Feb 24, 2011 at 02:14:07AM +0000, Jonathan A. Kollasch wrote:
> >> Hi,
> >>
> >> I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850
> >> board.  Raminit seems to go okay, as does the first bits of ramstage.
> >> However, ramstage fails after the first two passes through
> >> rs780_enable().  It stalls in get_vid_did() reading PCI config space
> >> of device 2 (or 4).  Also, the rs780 HT init code thinks the link should
> >> run at 200MHz, maybe that's related.
> >
> > Attached is the diff, and console output there from.
> > (Mainboard directory is a svn cp of bimini_fam10.)
> >
> 
> >rs780_htinit cpu_ht_freq=0.
> >rs780_htinit: HT1 mode
> 
> ]It looks it had problems getting the HT frequency from the CPU. Both
> ]sides have to agree on what is capable. You may need to look at the
> ]CPU HT code for a hint on why it reports what it does to the SB.
> ]
> ]Marc
> 
> Also remember that the family 10h swap list problem still exists.
> There are some old patches and discussion that might be useful.
> Here is an example:
> 
> http://www.mail-archive.com/coreboot@coreboot.org/msg27356.html

That seems to let it detect HT3 before warm reset, and the warm
reset succeeded, something that didn't happen when I attempted to
force HT3.  Unfortunately that didn't also fix the stall on
config space access.

	Jonathan Kollasch
Scott - 2011-02-24 19:15:05
Jonathan A. Kollasch wrote:

]That seems to let it detect HT3 before warm reset, and the warm
]reset succeeded, something that didn't happen when I attempted to
]force HT3.  Unfortunately that didn't also fix the stall on
]config space access.
]
]	Jonathan Kollasch

You could try disabling device 2 and 4 in devicetree.cb as a way
to see what other problems remain. I suppose you might need device
2 for a graphics card. It might be possible that some action is 
needed to turn on clocks or slot power. 

I also noticed the last line of rs780_ht.c references PCI device
ID 9600 (PCI_DEVICE_ID_AMD_RS780_HT). Not sure if revising that
is important.

Thanks,
Scott
Stefan Reinauer - 2011-02-24 21:34:05
* Scott Duplichan <scott@notabs.org> [110224 18:07]:
> -----Original Message-----
> From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Marc Jones
> Sent: Thursday, February 24, 2011 10:45 AM
> To: Jonathan A. Kollasch
> Cc: coreboot@coreboot.org
> Subject: Re: [coreboot] 870 attempt
> 
> On Thu, Feb 24, 2011 at 7:23 AM, Jonathan A. Kollasch
> <jakllsch@kollasch.net> wrote:
> > On Thu, Feb 24, 2011 at 02:14:07AM +0000, Jonathan A. Kollasch wrote:
> >> Hi,
> >>
> >> I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850
> >> board.  Raminit seems to go okay, as does the first bits of ramstage.
> >> However, ramstage fails after the first two passes through
> >> rs780_enable().  It stalls in get_vid_did() reading PCI config space
> >> of device 2 (or 4).  Also, the rs780 HT init code thinks the link should
> >> run at 200MHz, maybe that's related.
> >
> > Attached is the diff, and console output there from.
> > (Mainboard directory is a svn cp of bimini_fam10.)
> >
> 
> >rs780_htinit cpu_ht_freq=0.
> >rs780_htinit: HT1 mode
> 
> ]It looks it had problems getting the HT frequency from the CPU. Both
> ]sides have to agree on what is capable. You may need to look at the
> ]CPU HT code for a hint on why it reports what it does to the SB.
> ]
> ]Marc
> 
> Also remember that the family 10h swap list problem still exists.
> There are some old patches and discussion that might be useful.
> Here is an example:
> 
> http://www.mail-archive.com/coreboot@coreboot.org/msg27356.html

Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Scott - 2011-03-08 23:06:06
]> Also remember that the family 10h swap list problem still exists.
]> There are some old patches and discussion that might be useful.
]> Here is an example:
]> 
]> http://www.mail-archive.com/coreboot@coreboot.org/msg27356.html
]
] Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Thanks Stefen, rev 6439.
Thanks,
Scott

Patch

Index: src/southbridge/amd/rs780/rs780.c
===================================================================
--- src/southbridge/amd/rs780/rs780.c	(revision 6378)
+++ src/southbridge/amd/rs780/rs780.c	(working copy)
@@ -109,7 +109,11 @@ 
 
 static u32 get_vid_did(device_t dev)
 {
-	return pci_read_config32(dev, 0);
+	u32 vdid;
+	printk(BIOS_INFO, "gvd");
+	vdid = pci_read_config32(dev, 0);
+	printk(BIOS_INFO, "%08x\n", vdid);
+	return vdid;
 }
 
 static void rs780_nb_pci_table(device_t nb_dev)
Index: src/mainboard/asus/Kconfig
===================================================================
--- src/mainboard/asus/Kconfig	(revision 6378)
+++ src/mainboard/asus/Kconfig	(working copy)
@@ -37,6 +37,8 @@ 
 	bool "M4A785-M"
 config BOARD_ASUS_M4A78_EM
 	bool "M4A78-EM"
+config BOARD_ASUS_M4A87TD_USB3
+	bool "M4A87TD/USB3"
 config BOARD_ASUS_MEW_AM
 	bool "MEW-AM"
 config BOARD_ASUS_MEW_VM
@@ -64,6 +66,7 @@ 
 source "src/mainboard/asus/m2v-mx_se/Kconfig"
 source "src/mainboard/asus/m4a785-m/Kconfig"
 source "src/mainboard/asus/m4a78-em/Kconfig"
+source "src/mainboard/asus/m4a87td-usb3/Kconfig"
 source "src/mainboard/asus/mew-am/Kconfig"
 source "src/mainboard/asus/mew-vm/Kconfig"
 source "src/mainboard/asus/p2b/Kconfig"
Index: src/mainboard/asus/m4a87td-usb3/Kconfig
===================================================================
--- src/mainboard/asus/m4a87td-usb3/Kconfig	(revision 6375)
+++ src/mainboard/asus/m4a87td-usb3/Kconfig	(working copy)
@@ -1,9 +1,9 @@ 
-if BOARD_AMD_BIMINI_FAM10
+if BOARD_ASUS_M4A87TD_USB3
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_SOCKET_ASB2
+	select CPU_AMD_SOCKET_AM3
 	select DIMM_DDR3
 	select DIMM_REGISTERED
 	# TODO: Enable QRANK_DIMM_SUPPORT? Was commented in the Kconfig file,
@@ -24,16 +24,16 @@ 
 	select SERIAL_CPU_INIT
 	select AMDMCT
 	select GENERATE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_2048
+	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
 	select ENABLE_APIC_EXT_ID
-	select GFXUMA
+	#select GFXUMA
 	select HAVE_DEBUG_CAR
 	select SET_FIDVID
 
 config MAINBOARD_DIR
 	string
-	default amd/bimini_fam10
+	default asus/m4a87td-usb3
 
 config APIC_ID_OFFSET
 	hex
@@ -41,7 +41,7 @@ 
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "Bimini (Fam10)"
+	default "M4A87TD/USB3"
 
 config HW_MEM_HOLE_SIZEK
 	hex
@@ -93,14 +93,10 @@ 
 
 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 	hex
-	default 0x3060
+	default 0x8432
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
 
-endif #BOARD_AMD_BIMINI_FAM10
+endif #BOARD_ASUS_M4A87TD_USB3
Index: src/mainboard/asus/m4a87td-usb3/devicetree.cb
===================================================================
--- src/mainboard/asus/m4a87td-usb3/devicetree.cb	(revision 6375)
+++ src/mainboard/asus/m4a87td-usb3/devicetree.cb	(working copy)
@@ -1,7 +1,7 @@ 
 	# sample config for amd/bimini_fam10
 chip northbridge/amd/amdfam10/root_complex
 	device lapic_cluster 0 on
-		chip cpu/amd/socket_ASB2  #L1 and DDR3
+		chip cpu/amd/socket_AM3  #L1 and DDR3
 			 device lapic 0 on end
 		end
 	end
@@ -10,17 +10,17 @@ 
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
 					device pci 0.0 on end # HT  	0x9600
-					device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
-					device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
+					#device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
 					device pci 3.0 off end # PCIE P2P bridge	0x960b
 					device pci 4.0 on end # PCIE P2P bridge 0x9604
-					device pci 5.0 on end # PCIE P2P bridge 0x9605
-					device pci 6.0 on end # PCIE P2P bridge 0x9606
-					device pci 7.0 on end # PCIE P2P bridge 0x9607
+					device pci 5.0 off end # PCIE P2P bridge 0x9605
+					device pci 6.0 off end # PCIE P2P bridge 0x9606
+					device pci 7.0 off end # PCIE P2P bridge 0x9607
 					device pci 8.0 off end # NB/SB Link P2P bridge
 					device pci 9.0 on end #
-					device pci a.0 off end #
-					register "gppsb_configuration" = "4"   # Configuration E
+					device pci a.0 on end #
+					register "gppsb_configuration" = "1"   # Configuration E
 					register "gpp_configuration" = "2"   # Configuration C
 					register "port_enable" = "0x6fc"
 					register "gfx_dev2_dev3" = "1"
@@ -53,7 +53,24 @@ 
 					end # SM
 					device pci 14.1 on end # IDE    0x439c
 					device pci 14.2 on end # HDA    0x4383
-					device pci 14.3 on end # LPC	0x439d
+					device pci 14.3 on # LPC	0x439d
+						chip superio/ite/it8718f
+							device pnp 2e.0 off end
+							device pnp 2e.1 on
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.2 off end
+							device pnp 2e.3 off end
+							device pnp 2e.4 off end
+							device pnp 2e.5 off end
+							device pnp 2e.6 off end
+							device pnp 2e.7 off end
+							device pnp 2e.8 off end
+							device pnp 2e.9 off end
+							device pnp 2e.a off end
+						end #superio/ite/it8718f
+					end #LPC
 					device pci 14.4 off end # PCI	0x4384 # PCI-b conflict with GPIO.
 					device pci 14.5 on end # USB 2
 					device pci 14.6 on end # Gec
Index: src/mainboard/asus/m4a87td-usb3/romstage.c
===================================================================
--- src/mainboard/asus/m4a87td-usb3/romstage.c	(revision 6375)
+++ src/mainboard/asus/m4a87td-usb3/romstage.c	(working copy)
@@ -69,6 +69,7 @@ 
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
+#include "superio/ite/it8718f/early_serial.c"
 
 #define RC00  0
 #define RC01  1
@@ -109,6 +110,7 @@ 
 	enable_rs780_dev8();
 	sb800_lpc_init();
 
+	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
 #if CONFIG_USBDEBUG
 	sb800_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
Index: src/mainboard/asus/m4a87td-usb3/mainboard.c
===================================================================
--- src/mainboard/asus/m4a87td-usb3/mainboard.c	(revision 6375)
+++ src/mainboard/asus/m4a87td-usb3/mainboard.c	(working copy)
@@ -122,6 +122,7 @@ 
 }
 #endif	/* get_ide_dma66() */
 
+#if 0
 /*************************************************
 * enable the dedicated function in bimini board.
 * This function called early than rs780_enable.
@@ -178,6 +179,7 @@ 
 	enable_int_gfx();
 	/* get_ide_dma66(); */
 }
+#endif
 
 int add_mainboard_resources(struct lb_memory *mem)
 {
@@ -195,5 +197,5 @@ 
 
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("AMD Bimini Mainboard")
-	.enable_dev = bimini_enable,
+	//.enable_dev = bimini_enable,
 };