Patchwork Add NSC PC87364 support to superiotool

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Submitter Michael Karcher
Date 2011-03-02 22:30:21
Message ID <1299105021.4793.56.camel@localhost>
Download mbox | patch
Permalink /patch/2731/
State Accepted
Headers show

Comments

Michael Karcher - 2011-03-02 22:30:21
Hello jankeso,

in the process of writing a board enable procedure for your mainboard I
stumbled upon the fact that the chip used to control the write enable
line is most likely your Super I/O chip, which is a NSC PC87364.
superiotool currently does not support dumping that chip, so I can not
verify that indeed the GPIO port of the Super I/O chip is accessed (at
address 0x80C). I attached a patch to dump the contents of that chip to
this mail. Please apply that patch to current superiotool CVS sources
(to be obtained from svn://coreboot.org/repos/trunk/util/superiotool)
and attach the output to a reply to this mail or upload to
paste.flashrom.org.

This mail has been cc'ed to the coreboot list for getting this patch
included into superiotool. If something is wrong with that patch, please
Cc: me, as I am not subscribed to the coreboot list. Thanks.

Regards,
  Michael Karcher
Michał Janke - 2011-03-03 18:03:46
Hi Michael,

seems to me that the GPIO is accessed as you predicted. I attach the
output of superiorool -deV.

Regards,
Michal

2011/3/2 Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>:
> Hello jankeso,
>
> in the process of writing a board enable procedure for your mainboard I
> stumbled upon the fact that the chip used to control the write enable
> line is most likely your Super I/O chip, which is a NSC PC87364.
> superiotool currently does not support dumping that chip, so I can not
> verify that indeed the GPIO port of the Super I/O chip is accessed (at
> address 0x80C). I attached a patch to dump the contents of that chip to
> this mail. Please apply that patch to current superiotool CVS sources
> (to be obtained from svn://coreboot.org/repos/trunk/util/superiotool)
> and attach the output to a reply to this mail or upload to
> paste.flashrom.org.
>
> This mail has been cc'ed to the coreboot list for getting this patch
> included into superiotool. If something is wrong with that patch, please
> Cc: me, as I am not subscribed to the coreboot list. Thanks.
>
> Regards,
>  Michael Karcher
>
superiotool r4668
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0x0587, id=0x11e4
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x2e...
  Failed. Returned data: id=0xe411, rev=0xc
Probing for ITE Super I/O (init=it8761e) at 0x2e...
  Failed. Returned data: id=0xe411, rev=0xc
Probing for ITE Super I/O (init=it8228e) at 0x2e...
  Failed. Returned data: id=0xe411, rev=0xc
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id=0xe411, rev=0xc
Probing for ITE Super I/O (init=standard) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
Found NSC PC87364 (sid=0xe4, srid=0x0b) at 0x2e
Register dump:
idx 20 21 22 23 24 25 26 27  28 2a 2b 2c 2d 2e
val e4 11 3c 87 05 00 00 0b  00 5b 1b 38 85 00
def e4 11 00 03 00 00 00 NA  00 MM 00 00 NA RR
LDN 0x00 (Floppy)
idx 30 60 61 70 71 74 75 f0  f1
val 00 03 f2 06 03 02 04 24  00
def 00 03 f2 06 03 02 04 24  00
LDN 0x01 (Parallel port)
idx 30 60 61 70 71 74 75 f0
val 01 03 78 07 02 03 04 92
def 00 02 78 07 02 04 04 f2
LDN 0x02 (COM2)
idx 30 60 61 70 71 74 75 f0
val 00 02 f8 03 03 04 04 02
def 00 02 f8 03 03 04 04 02
LDN 0x03 (COM1)
idx 30 60 61 70 71 74 75 f0
val 01 03 f8 04 03 04 04 02
def 00 03 f8 04 03 04 04 02
LDN 0x04 (System wake-up control (SWC))
idx 30 60 61 70 71 74 75
val 01 08 40 00 03 04 04
def 00 00 00 00 03 04 04
LDN 0x05 (Mouse)
idx 30 70 71 74 75
val 01 0c 02 04 04
def 00 0c 02 04 04
LDN 0x06 (Keyboard)
idx 30 60 61 62 63 70 71 74  75 f0
val 01 00 60 00 64 01 02 04  04 40
def 01 00 60 00 64 01 02 04  04 40
LDN 0x07 (GPIO)
idx 30 60 61 70 71 74 75 f0  f1 f2
val 01 08 00 00 03 04 04 46  17 00
def 00 00 00 00 03 04 04 00  00 00
LDN 0x08 (ACCESS.bus (ACB))
idx 30 60 61 70 71 74 75 f0
val 00 00 00 00 03 04 04 00
def 00 00 00 00 03 04 04 00
LDN 0x09 (Fan speed control and monitor (FSCM))
idx 30 60 61 70 71 74 75 f0  f1
val 01 08 10 00 03 04 04 6c  00
def 00 00 00 00 03 04 04 00  00
LDN 0x0a (Watchdog timer)
idx 30 60 61 70 71 74 75 f0
val 00 00 00 00 03 04 04 02
def 00 00 00 00 03 04 04 02
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
  Failed. Returned data: id=0xe4, rev=0x11
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xe4/0x00, rev=0x11
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xe4/0x00, rev=0x11
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xe4/0x00, rev=0x11
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id/oldid=0xe4/0x00, rev=0x11
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Stefan Reinauer - 2011-03-04 03:49:25
* Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> [110302 23:30]:
> Hello jankeso,
> 
> in the process of writing a board enable procedure for your mainboard I
> stumbled upon the fact that the chip used to control the write enable
> line is most likely your Super I/O chip, which is a NSC PC87364.
> superiotool currently does not support dumping that chip, so I can not
> verify that indeed the GPIO port of the Super I/O chip is accessed (at
> address 0x80C). I attached a patch to dump the contents of that chip to
> this mail. Please apply that patch to current superiotool CVS sources
> (to be obtained from svn://coreboot.org/repos/trunk/util/superiotool)
> and attach the output to a reply to this mail or upload to
> paste.flashrom.org.
> 
> This mail has been cc'ed to the coreboot list for getting this patch
> included into superiotool. If something is wrong with that patch, please
> Cc: me, as I am not subscribed to the coreboot list. Thanks.
> 
> Regards,
>   Michael Karcher

> Add National Semiconductors PC87364.
> 
> Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Carl-Daniel Hailfinger - 2011-03-04 19:22:53
Auf 04.03.2011 04:49, Stefan Reinauer schrieb:
> * Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> [110302 23:30]:
>   
>> Add National Semiconductors PC87364.
>>
>> Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
>>     
> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
>   

Michael, AFAIK the flashrom and coreboot repositories have the same user
rights, so in theory you should be able to commit.

Regards,
Carl-Daniel
Michael Karcher - 2011-03-05 23:53:03
Hello coreboot developers,

> >> Add National Semiconductors PC87364.
> >> Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
> > Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
> Michael, AFAIK the flashrom and coreboot repositories have the same user
> rights, so in theory you should be able to commit.

how would you like me to proceed? Technically I most likely have commit
rights to that repo, but I never felt as coreboot developer and don't
read the coreboot mailing list. Should I nevertheless commit myself or
should I have some coreboot guy commit that patch?

Regards,
  Michael Karcher
Alexandru Gagniuc - 2011-03-06 14:01:15
On 03/06/2011 01:53 AM, Michael Karcher wrote:
> Hello coreboot developers,
> 
>>>> Add National Semiconductors PC87364.
>>>> Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
>>> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
>> Michael, AFAIK the flashrom and coreboot repositories have the same user
>> rights, so in theory you should be able to commit.
> 
> how would you like me to proceed? Technically I most likely have commit
> rights to that repo, but I never felt as coreboot developer and don't
> read the coreboot mailing list. Should I nevertheless commit myself or
> should I have some coreboot guy commit that patch?
> 
It was acked by Stefan. I think you can confidently commit.

Alex
Paul Menzel - 2011-03-06 14:35:23
Dear Michael,


I am adding you back to CC.

Am Sonntag, den 06.03.2011, 16:01 +0200 schrieb Alex G.:
> On 03/06/2011 01:53 AM, Michael Karcher wrote:

> >>>> Add National Semiconductors PC87364.
> >>>> Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
> >>> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
> >> Michael, AFAIK the flashrom and coreboot repositories have the same user
> >> rights, so in theory you should be able to commit.
> > 
> > how would you like me to proceed? Technically I most likely have commit
> > rights to that repo, but I never felt as coreboot developer and don't
> > read the coreboot mailing list. Should I nevertheless commit myself or
> > should I have some coreboot guy commit that patch?

> It was acked by Stefan. I think you can confidently commit.

I would also say that you can commit.

And Michael, why not become a coreboot developer and port your
motherboard. You would be warmly welcomed. ;-)


Thanks,

Paul
Carl-Daniel Hailfinger - 2011-03-06 18:01:46
Auf 04.03.2011 20:22, Carl-Daniel Hailfinger schrieb:
> Auf 04.03.2011 04:49, Stefan Reinauer schrieb:
>   
>> * Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> [110302 23:30]:
>>   
>>     
>>> Add National Semiconductors PC87364.
>>>
>>> Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
>>>     
>>>       
>> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
>>   
>>     
> Michael, AFAIK the flashrom and coreboot repositories have the same user
> rights, so in theory you should be able to commit.
>   

Sorry about the confusion.

Thanks for your patch!
Committed to the coreboot repo in revision 6433.

Regards,
Carl-Daniel

Patch

Add National Semiconductors PC87364.

Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>

Index: nsc.c
===================================================================
--- nsc.c	(Revision 6426)
+++ nsc.c	(Arbeitskopie)
@@ -242,6 +242,48 @@ 
 			{0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x00,EOT}},
 		{EOT}}},
 	{0xe4, "PC87364", {
+		{NOLDN, NULL,
+			{0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x2a,
+			 0x2b,0x2c,0x2d,0x2e,EOT},
+			{0xe4,0x11,0x00,0x03,0x00,0x00,0x00,NANA,0x00,MISC,
+			 0x00,0x00,NANA,RSVD,EOT}},
+		{0x0, "Floppy",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT},
+			{0x00,0x03,0xf2,0x06,0x03,0x02,0x04,0x24,0x00,EOT}},
+		{0x1, "Parallel port",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+			{0x00,0x02,0x78,0x07,0x02,0x04,0x04,0xf2,EOT}},
+		{0x2, "COM2",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+			{0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}},
+		{0x3, "COM1",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+			{0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}},
+		{0x4, "System wake-up control (SWC)",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT},
+			{0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}},
+		{0x5, "Mouse",
+			{0x30,0x70,0x71,0x74,0x75,EOT},
+			{0x00,0x0c,0x02,0x04,0x04,EOT}},
+		{0x6, "Keyboard",
+			{0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,0xf0,
+			 EOT},
+			{0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x04,0x04,0x40,
+			 EOT}},
+		{0x7, "GPIO",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2,
+			 EOT},
+			{0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,0x00,0x00,
+			 EOT}},
+		{0x8, "ACCESS.bus (ACB)",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+			{0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,EOT}},
+		{0x9, "Fan speed control and monitor (FSCM)",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT},
+			{0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,0x00,EOT}},
+		{0xa, "Watchdog timer",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+			{0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x02,EOT}},
 		{EOT}}},
 	{0xe5, "PC87365", {	/* SRID[7..0] == chip revision */
 		{EOT}}},