Patchwork [The,604,CAR,crusades] Episode VI - Return of the Patcher

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Submitter Alexandru Gagniuc
Date 2011-03-09 23:28:25
Message ID <4D780D19.4010306@gmail.com>
Download mbox | patch
Permalink /patch/2765/
State New
Headers show

Comments

Alexandru Gagniuc - 2011-03-09 23:28:25
I hope you don't mind my submitting two patches in one email. I'm
running out of titles to inspire myself from.

Alex

Patch

Remove unused variables, and add a declaration for
sdram_initialize() for the Intel e7525 northbridge.

This allows the e7525 to be used in CAR boards.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

Index: src/northbridge/intel/e7525/raminit.c
===================================================================
--- src/northbridge/intel/e7525/raminit.c	(revision 6429)
+++ src/northbridge/intel/e7525/raminit.c	(working copy)
@@ -2,6 +2,7 @@ 
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman
+ * Copyright (C) 2011  Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -659,7 +660,7 @@ 
 
 	goto out;
 
- val_err:
+/* val_err: */
 	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
@@ -780,7 +781,6 @@ 
 	unsigned int dimm;
 	unsigned int edge;
 	int32_t data32;
-	uint32_t data32_dram;
 	uint32_t dcal_data32_0;
 	uint32_t dcal_data32_1;
 	uint32_t dcal_data32_2;
@@ -1013,10 +1013,6 @@ 
 	uint32_t data32;
 	uint32_t mode_reg;
 	uint32_t *iptr;
-	volatile unsigned long *iptrv;
-	msr_t msr;
-	uint32_t scratch;
-	uint8_t byte;
 	uint16_t data16;
 	static const struct {
 		uint32_t clkgr[4];
@@ -1067,8 +1063,8 @@ 
 	data32 = data32 | (1 << 5);  /* temp turn off of ODT */
   	/* Set gearing, then dram controller mode */
   	/* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */
-  	for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0;
-			cnt<4;cnt++) {
+	iptr = (uint32_t*) gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr;
+  	for(cnt=0; cnt<4; cnt++) {
   		pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
 	}
 	/* 0x7c DRC */
Index: src/northbridge/intel/e7525/raminit.h
===================================================================
--- src/northbridge/intel/e7525/raminit.h	(revision 6429)
+++ src/northbridge/intel/e7525/raminit.h	(working copy)
@@ -1,3 +1,23 @@ 
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2011  Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 #ifndef RAMINIT_H
 #define RAMINIT_H
 
@@ -9,4 +29,12 @@ 
 	uint16_t channel1[DIMM_SOCKETS];
 };
 
+#ifndef __ROMCC__
+#if defined(__PRE_RAM__) && CONFIG_RAMINIT_SYSINFO
+void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo);
+#else
+void sdram_initialize(int controllers, const struct mem_controller *ctrl);
+#endif
+#endif /* ROMCC */
+
 #endif /* RAMINIT_H */