Patchwork [7/8] check if write enable is really set in nicintel_spi_init (and minor comment changes).

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Submitter Stefan Tauner
Date 2011-03-15 15:29:15
Message ID <24e35011e614961584ddaca4f32fa85e448ee57f.1300202693.git.stefan.tauner@student.tuwien.ac.at>
Download mbox | patch
Permalink /patch/2791/
State Accepted
Commit r1510
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Comments

Stefan Tauner - 2011-03-15 15:29:15
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
---
 nicintel_spi.c |   15 +++++++++++++--
 1 files changed, 13 insertions(+), 2 deletions(-)
Idwer Vollering - 2012-02-20 18:49:06
2011/3/15 Stefan Tauner <stefan.tauner@student.tuwien.ac.at>:
> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>

Adding "pci_mmio_writel(FLASH_WRITES_DISABLED, nicintel_spibar +
EECD);" right after the usage of register_shutdown() works as it
should:

Initializing nicintel_spi programmer
Found "Intel 82541PI Gigabit Ethernet Controller" (8086:107c, BDF 01:01.0).
Requested BAR is MEM, 32bit, not prefetchable
Enabling flash write access failed.
Error: Programmer initialization failed.

Acked-by: Idwer Vollering <vidwer@gmail.com>

> ---
>  nicintel_spi.c |   15 +++++++++++++--
>  1 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/nicintel_spi.c b/nicintel_spi.c
> index 811ed6e..88d86af 100644
> --- a/nicintel_spi.c
> +++ b/nicintel_spi.c
> @@ -34,11 +34,14 @@
>
>  #define MEMMAP_SIZE getpagesize()
>
> +/* EEPROM/Flash Control & Data Register */
>  #define EECD   0x10
> +/* Flash Access Register */
>  #define FLA    0x1c
>
>  /*
>  * Register bits of EECD.
> + * Table 13-6
>  *
>  * Bit 04, 05: FWE (Flash Write Enable Control)
>  * 00b = not allowed
> @@ -49,8 +52,9 @@
>  #define FLASH_WRITES_DISABLED  0x10 /* FWE: 10000b */
>  #define FLASH_WRITES_ENABLED   0x20 /* FWE: 100000b */
>
> -/* Flash Access register bits */
> -/* Table 13-9 */
> +/* Flash Access register bits
> + * Table 13-9
> + */
>  #define FL_SCK 0
>  #define FL_CS  1
>  #define FL_SI  2
> @@ -157,6 +161,13 @@ int nicintel_spi_init(void)
>        tmp |= FLASH_WRITES_ENABLED;
>        pci_mmio_writel(tmp, nicintel_spibar + EECD);
>
> +       /* test if FWE is really set to allow writes */
> +       tmp = pci_mmio_readl(nicintel_spibar + EECD);
> +       if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp & FLASH_WRITES_ENABLED) ) {
> +               msg_perr("Enabling flash write access failed.\n");
> +               return 1;
> +       }
> +
>        /* 1 usec halfperiod delay for now. */
>        if (bitbang_spi_init(&bitbang_spi_master_nicintel, 1))
>                return 1;
> --
> 1.7.1
>
>
> _______________________________________________
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> flashrom@flashrom.org
> http://www.flashrom.org/mailman/listinfo/flashrom
Stefan Tauner - 2012-02-27 19:55:11
On Mon, 20 Feb 2012 19:49:06 +0100
Idwer Vollering <vidwer@gmail.com> wrote:

> 2011/3/15 Stefan Tauner <stefan.tauner@student.tuwien.ac.at>:
> > Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
> 
> Adding "pci_mmio_writel(FLASH_WRITES_DISABLED, nicintel_spibar +
> EECD);" right after the usage of register_shutdown() works as it
> should:
> 
> Initializing nicintel_spi programmer
> Found "Intel 82541PI Gigabit Ethernet Controller" (8086:107c, BDF 01:01.0).
> Requested BAR is MEM, 32bit, not prefetchable
> Enabling flash write access failed.
> Error: Programmer initialization failed.
> 
> Acked-by: Idwer Vollering <vidwer@gmail.com>

thanks!
committed in r1510

Patch

diff --git a/nicintel_spi.c b/nicintel_spi.c
index 811ed6e..88d86af 100644
--- a/nicintel_spi.c
+++ b/nicintel_spi.c
@@ -34,11 +34,14 @@ 
 
 #define MEMMAP_SIZE getpagesize()
 
+/* EEPROM/Flash Control & Data Register */
 #define EECD	0x10
+/* Flash Access Register */
 #define FLA	0x1c
 
 /*
  * Register bits of EECD.
+ * Table 13-6
  * 
  * Bit 04, 05: FWE (Flash Write Enable Control)
  * 00b = not allowed
@@ -49,8 +52,9 @@ 
 #define FLASH_WRITES_DISABLED	0x10 /* FWE: 10000b */
 #define FLASH_WRITES_ENABLED	0x20 /* FWE: 100000b */
 
-/* Flash Access register bits */
-/* Table 13-9 */
+/* Flash Access register bits
+ * Table 13-9
+ */
 #define FL_SCK	0
 #define FL_CS	1
 #define FL_SI	2
@@ -157,6 +161,13 @@  int nicintel_spi_init(void)
 	tmp |= FLASH_WRITES_ENABLED;
 	pci_mmio_writel(tmp, nicintel_spibar + EECD);
 
+	/* test if FWE is really set to allow writes */
+	tmp = pci_mmio_readl(nicintel_spibar + EECD);
+	if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp & FLASH_WRITES_ENABLED) ) {
+		msg_perr("Enabling flash write access failed.\n");
+		return 1;
+	}
+
 	/* 1 usec halfperiod delay for now. */
 	if (bitbang_spi_init(&bitbang_spi_master_nicintel, 1))
 		return 1;