===================================================================
@@ -33,6 +33,8 @@
bool "M2V"
config BOARD_ASUS_M2V_MX_SE
bool "M2V-MX SE"
+config BOARD_ASUS_M4A77TD_PRO
+ bool "M4A77TD-PRO"
config BOARD_ASUS_M4A785M
bool "M4A785-M"
config BOARD_ASUS_M4A78_EM
@@ -62,6 +64,7 @@
source "src/mainboard/asus/m2n-e/Kconfig"
source "src/mainboard/asus/m2v/Kconfig"
source "src/mainboard/asus/m2v-mx_se/Kconfig"
+source "src/mainboard/asus/m4a77td-pro/Kconfig"
source "src/mainboard/asus/m4a785-m/Kconfig"
source "src/mainboard/asus/m4a78-em/Kconfig"
source "src/mainboard/asus/mew-am/Kconfig"
===================================================================
@@ -1,4 +1,4 @@
-if BOARD_AMD_TILAPIA_FAM10
+if BOARD_ASUS_M4A77TD_PRO
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@@ -9,7 +9,7 @@
select NORTHBRIDGE_AMD_AMDFAM10
select SOUTHBRIDGE_AMD_RS780
select SOUTHBRIDGE_AMD_SB700
- select SUPERIO_ITE_IT8718F
+ select SUPERIO_ITE_IT8712F
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
@@ -22,14 +22,15 @@
select AMDMCT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
- select RAMINIT_SYSINFO
select ENABLE_APIC_EXT_ID
select GFXUMA
- select QRANK_DIMM_SUPPORT
+ select SVI_HIGH_FREQ
+ select RAMINIT_SYSINFO
+ select QRANK_DIMM_SUPPORT
config MAINBOARD_DIR
string
- default amd/tilapia_fam10
+ default asus/m4a77td-pro
config APIC_ID_OFFSET
hex
@@ -37,15 +38,15 @@
config MAINBOARD_PART_NUMBER
string
- default "Tilapia (Fam10)"
+ default "M4A77TD-PRO (Fam10)"
config MAX_CPUS
int
- default 8
+ default 6
config MAX_PHYSICAL_CPUS
int
- default 2
+ default 1
config MEM_TRAIN_SEQ
int
@@ -65,7 +66,7 @@
config IRQ_SLOT_COUNT
int
- default 11
+ default 19
config AMD_UCODE_PATCH_FILE
string
===================================================================
@@ -11,21 +11,20 @@
device pci 18.0 on # northbridge
chip southbridge/amd/rs780
device pci 0.0 on end # HT 0x9600
- device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
device pci 3.0 on end # PCIE P2P bridge 0x960b
device pci 4.0 on end # PCIE P2P bridge 0x9604
device pci 5.0 off end # PCIE P2P bridge 0x9605
device pci 6.0 off end # PCIE P2P bridge 0x9606
device pci 7.0 off end # PCIE P2P bridge 0x9607
- device pci 8.0 off end # NB/SB Link P2P bridge
- device pci 9.0 on end #
+ device pci 8.0 off end
+ device pci 9.0 off end #
device pci a.0 on end #
register "gppsb_configuration" = "1" # Configuration B
register "gpp_configuration" = "3" # Configuration D default
register "port_enable" = "0x6fc"
register "gfx_dev2_dev3" = "1"
- register "gfx_dual_slot" = "2"
+ register "gfx_dual_slot" = "0"
register "gfx_lane_reversal" = "0"
register "gfx_tmds" = "0"
@@ -58,7 +57,7 @@
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
- chip superio/ite/it8718f
+ chip superio/ite/it8712
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
@@ -76,7 +75,7 @@
io 0x60 = 0x378
irq 0x70 = 7
end
- device pnp 2e.4 off end # EC
+ device pnp 2e.4 off end # EC
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
@@ -109,7 +108,6 @@
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
-# device pci 00.5 on end
end
end #pci_domain
#for node 32 to node 63
===================================================================
@@ -42,7 +42,10 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/ite/it8718f/early_serial.c"
+
+static int smbus_read_byte(u32 device, u32 address);
+
+#include "superio/ite/it8712f/early_serial.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
@@ -51,6 +54,9 @@
#include "southbridge/amd/sb700/early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
@@ -72,6 +78,7 @@
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
+#include "southbridge/amd/sb700/early_setup.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -93,7 +100,13 @@
post_code(0x30);
if (bist == 0) {
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
+ #if CONFIG_RAMINIT_SYSINFO
+ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
+ #else
+ bsp_apicid = init_cpus(cpu_init_detectedx); /* mmconf is inited in init_cpus */
+ #endif
+
+
/* All cores run this but the BSP(node0,core0) is the only core that returns. */
}
@@ -102,7 +115,8 @@
enable_rs780_dev8();
sb700_lpc_init();
- it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
+ it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ it8712f_kill_watchdog();
uart_init();
#if CONFIG_USBDEBUG
@@ -166,6 +180,7 @@
/* run _early_setup before soft-reset. */
rs780_early_setup();
+ printk(BIOS_DEBUG, "after rs780 early setup\n");
sb700_early_setup();
#if CONFIG_SET_FIDVID
@@ -192,7 +207,6 @@
#endif
rs780_htinit();
-
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
print_info("...WARM RESET...\n\n\n");
@@ -210,6 +224,9 @@
// die("Die Before MCT init.");
+ dump_spd_registers(&sysinfo->ctrl[0]);
+ dump_smbus_registers();
+
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
post_code(0x41);
@@ -253,15 +270,12 @@
*/
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
{
- static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+ static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
/* If the BUID was adjusted in early_ht we need to do the manual override */
- if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
- printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
if ((node == 0) && (link == 0)) { /* BSP SB link */
*List = swaplist;
return 1;
}
- }
return 0;
}
===================================================================
@@ -1,11 +1,12 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 Xavi Drudis Ferran <xdrudis@tinet.cat>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -17,96 +18,49 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
+
#include <arch/pirq_routing.h>
-#include <cpu/amd/amdfam10_sysconf.h>
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * 19, /* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x14 << 3) | 0x3, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x1002, /* Vendor */
+ 0x439d, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xcb, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x02 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x01, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x2, 0x0},
+ {0x00, (0x03 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x04 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x05 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x06 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x07 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x09 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x0a << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x02, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0xa, 0x0},
+ {0x00, (0x0b << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x0c << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x14 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x12 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x13 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x11 << 3) | 0x0, {{0x0c, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x03, (0x05 << 3) | 0x0, {{0x0a, 0xdc90}, {0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}}, 0xc, 0x0},
+ {0x03, (0x06 << 3) | 0x0, {{0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}, {0x0a, 0xdc90}}, 0xd, 0x0},
+ {0x03, (0x07 << 3) | 0x0, {{0x0c, 0xdc90}, {0x0d, 0xdc90}, {0x0a, 0xdc90}, {0x0b, 0xdc90}}, 0xe, 0x0},
+ }
+};
-
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
- u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
- u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
- u8 slot, u8 rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-extern u8 bus_rs780[8];
-extern u8 bus_sb700[2];
-extern unsigned long sbdn_sb700;
-
unsigned long write_pirq_routing_table(unsigned long addr)
{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- u32 slot_num;
- u8 *v;
-
- u8 sum = 0;
- int i;
-
- get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be betweeen 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (u8 *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_sb700[0];
- pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1002;
- pirq->rtr_device = 0x4384;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* pci bridge */
- write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
- return (unsigned long)pirq_info;
+ return copy_pirq_routing_table(addr);
}
===================================================================
@@ -22,8 +22,8 @@
"DSDT.AML", /* Output filename */
"DSDT", /* Signature */
0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "AMD ", /* OEMID */
- "TILAPIA ", /* TABLE ID */
+ "ASUS ", /* OEMID */
+ "M4A77TDP", /* TABLE ID */
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */
@@ -1168,7 +1168,7 @@
/* Note: Only need HID on Primary Bus */
Device(PCI0) {
External (TOM1)
- External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
+ External (TOM2)
Name(_HID, EISAID("PNP0A03"))
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
Method(_BBN, 0) { /* Bus number = 0 */
@@ -1366,7 +1366,7 @@
/* Real Time Clock Device */
Device(RTC0) {
- Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
+ Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
Name(_CRS, ResourceTemplate() {
IRQNoFlags(){8}
IO(Decode16,0x0070, 0x0070, 0, 2)
@@ -1450,7 +1450,7 @@
Name(_ADR, 0x00140006)
} /* end Ac97modem */
- /* ITE8718 Support */
+ /* ITE8718 Support TODO : it's ITE8712 for M4A77TD-PRO*/
OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
Field (IOID, ByteAcc, NoLock, Preserve)
{
@@ -1614,8 +1614,7 @@
/*
* If(LNotEqual(TOM2, 0x00000000)){
* Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * ShiftLeft(TOM2, 20, Local0)
- * Subtract(Local0, 0x100000000, DMHL)
+ * Subtract(TOM2, 0x100000000, DMHL)
* }
*/
===================================================================
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * is_dev3_present() (C) 2010 Qing Pei Wang <wangqingpei@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -26,6 +27,7 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
+#include <southbridge/amd/rs780/rs780.h>
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
@@ -49,7 +51,6 @@
void set_pcie_dereset(void);
void set_pcie_reset(void);
u8 is_dev3_present(void);
-
void set_pcie_dereset()
{
u8 byte;
@@ -130,7 +131,7 @@
}
#endif
-/*
+ /*
* justify the dev3 is exist or not
*/
u8 is_dev3_present(void)
@@ -160,61 +161,6 @@
/*
- * set gpio40 gfx
- */
-static void set_gpio40_gfx(void)
-{
- u8 byte;
- u32 dword;
- device_t sm_dev;
- /* disable the GPIO40 as CLKREQ2# function */
- byte = pm_ioread(0xd3);
- byte &= ~(1 << 7);
- pm_iowrite(0xd3, byte);
-
- /* disable the GPIO40 as CLKREQ3# function */
- byte = pm_ioread(0xd4);
- byte &= ~(1 << 0);
- pm_iowrite(0xd4, byte);
-
- /* enable pull up for GPIO68 */
- byte = pm2_ioread(0xf1);
- byte &= ~(1 << 4);
- pm2_iowrite(0xf1, byte);
-
- /* access the smbus extended register */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- /*if the dev3 is present, set the gfx to 2x8 lanes*/
- /*otherwise set the gfx to 1x16 lanes*/
- if(is_dev3_present()){
-
- printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n");
- /* when the gpio40 is configured as GPIO, this will enable the output */
- pci_write_config32(sm_dev, 0xf8, 0x4);
- dword = pci_read_config32(sm_dev, 0xfc);
- dword &= ~(1 << 10);
-
- /* When the gpio40 is configured as GPIO, this will represent the output value*/
- /* 1 :enable two x8 , 0 : master slot enable only */
- dword |= (1 << 26);
- pci_write_config32(sm_dev, 0xfc, dword);
-
- }else{
- printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
- /* when the gpio40 is configured as GPIO, this will enable the output */
- pci_write_config32(sm_dev, 0xf8, 0x4);
- dword = pci_read_config32(sm_dev, 0xfc);
- dword &= ~(1 << 10);
-
- /* When the gpio40 is configured as GPIO, this will represent the output value*/
- /* 1 :enable two x8 , 0 : master slot enable only */
- dword &= ~(1 << 26);
- pci_write_config32(sm_dev, 0xfc, dword);
- }
-}
-
-/*
* set thermal config
*/
static void set_thermal_config(void)
@@ -278,13 +224,90 @@
*/
}
+/*
+ * set gpio40 gfx
+ */
+static void set_gpio40_gfx(void)
+{
+ u8 byte;
+ u32 dword;
+ device_t sm_dev;
+ /* disable the GPIO40 as CLKREQ2# function */
+ byte = pm_ioread(0xd3);
+ byte &= ~(1 << 7);
+ pm_iowrite(0xd3, byte);
+
+ /* disable the GPIO40 as CLKREQ3# function */
+ byte = pm_ioread(0xd4);
+ byte &= ~(1 << 0);
+ pm_iowrite(0xd4, byte);
+
+ /* enable pull up for GPIO68 */
+ byte = pm2_ioread(0xf1);
+ byte &= ~(1 << 4);
+ pm2_iowrite(0xf1, byte);
+
+ /* access the smbus extended register */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ /*if the dev3 is present, set the gfx to 2x8 lanes*/
+ /*otherwise set the gfx to 1x16 lanes*/
+ if(is_dev3_present()){
+
+ printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n");
+ /* when the gpio40 is configured as GPIO, this will enable the output */
+ pci_write_config32(sm_dev, 0xf8, 0x4);
+ dword = pci_read_config32(sm_dev, 0xfc);
+ dword &= ~(1 << 10);
+
+ /* When the gpio40 is configured as GPIO, this will represent the output value*/
+ /* 1 :enable two x8 , 0 : master slot enable only */
+ dword |= (1 << 26);
+ pci_write_config32(sm_dev, 0xfc, dword);
+
+ }else{
+ printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
+ /* when the gpio40 is configured as GPIO, this will enable the output */
+ pci_write_config32(sm_dev, 0xf8, 0x4);
+ dword = pci_read_config32(sm_dev, 0xfc);
+ dword &= ~(1 << 10);
+
+ /* When the gpio40 is configured as GPIO, this will represent the output value*/
+ /* 1 :enable two x8 , 0 : master slot enable only */
+ dword &= ~(1 << 26);
+ pci_write_config32(sm_dev, 0xfc, dword);
+ }
+}
+
+/* override the default SATA PHY setup */
+void sb700_setup_sata_phys(struct device *dev) {
+ /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
+ pci_write_config16(dev, 0x86, 0x2c00);
+
+ /* RPR7.6.2 SATA GENI PHY ports setting */
+ pci_write_config32(dev, 0x88, 0x01B48016);
+ pci_write_config32(dev, 0x8c, 0x01B48016);
+ pci_write_config32(dev, 0x90, 0x01B48016);
+ pci_write_config32(dev, 0x94, 0x01B48019); /* SATA4 = eSATA */
+ pci_write_config32(dev, 0x98, 0x01B48016);
+ pci_write_config32(dev, 0x9C, 0x01B48016);
+
+ /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
+ pci_write_config16(dev, 0xA0, 0xA07A);
+ pci_write_config16(dev, 0xA2, 0xA07A);
+ pci_write_config16(dev, 0xA4, 0xA07A);
+ pci_write_config16(dev, 0xA6, 0xA09F); /* SATA4 = eSATA */
+ pci_write_config16(dev, 0xA8, 0xA07A);
+ pci_write_config16(dev, 0xAA, 0xA07A);
+}
+
/*************************************************
-* enable the dedicated function in tilapia board.
+* enable the dedicated function in m4a77td-pro board.
* This function called early than rs780_enable.
*************************************************/
-static void tilapia_enable(device_t dev)
+static void m4a77tdpro_enable(device_t dev)
{
- printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev);
+ printk(BIOS_INFO, "Mainboard M4A77TD-PRO Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
msr_t msr, msr2;
@@ -329,6 +352,7 @@
/* get_ide_dma66(); */
set_thermal_config();
set_gpio40_gfx();
+
}
int add_mainboard_resources(struct lb_memory *mem)
@@ -346,6 +370,6 @@
}
struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD TILAPIA Mainboard")
- .enable_dev = tilapia_enable,
+ CHIP_NAME("ASUS M4A77TD-PRO Mainboard")
+ .enable_dev = m4a77tdpro_enable,
};