Patchwork 440BX registered SDRAM support

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Submitter Keith Hui
Date 2011-03-27 12:36:38
Message ID <AANLkTinZ7gZXJe87dWeX-9bH3vYiKVe7CVYUZg-Jx9Z7@mail.gmail.com>
Download mbox | patch
Permalink /patch/2814/
State Superseded
Headers show

Comments

Keith Hui - 2011-03-27 12:36:38
See attached for patch with sign-off inside. Boot tested on ASUS
P2B-LS with both regular and registered ECC modules.

Now that I got some registered ECC modules in, I am able to code up
this patch to allow registered SDRAM to initialize. This is needed in
advance of ECC support because most ECC modules are registered. The
same modules I have also happened to be electrically "256MB single
side" so I am finally able to, unfortunately, exercise the "set it
smaller so at least I can use it" patch of r5508.

ECC is still not enabled in this patch. That would be for a separate patch.

Enjoy
Keith
Adds support for initializing registered SDRAM modules on Intel 440BX northbridge.

Signed-off-by: Keith Hui <buurin@gmail.com>
Stefan Reinauer - 2011-03-28 01:22:11
On 3/27/11 5:36 AM, Keith Hui wrote:
> Adds support for initializing registered SDRAM modules on Intel 440BX 
> northbridge.
>
> Signed-off-by: Keith Hui <buurin@gmail.com>
>
> Index: src/northbridge/intel/i440bx/raminit.c
> ===================================================================
> --- src/northbridge/intel/i440bx/raminit.c    (revision 6460)
> +++ src/northbridge/intel/i440bx/raminit.c    (working copy)
>
> +    /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM/Registered 
> SDRAM). */
> +
> +    if ((edosd & 0x84) == 0x84) {
> +        edosd = 0x10; // Registered SDRAM
> +    } else {
> +        // Clear [4:3] in case it's EDO.
> +        edosd &= 0x07;
> +//    } else if (edosd & 0x02) {
Besides being commented out, this piece of code would never be executed, 
as there already is an else case.
Also, modifying edosd in place is semi nice.

Please clean this up before committing. Maybe consider using switch/case?

Looks good otherwise.
> +//        edosd |= 0x00;
> +        if (edosd & 0x04) {
> +            edosd |= 0x08; // SDRAM
> +        }
>      }
> +    // Keep only [4:3].
>      edosd &= 0x18;
>
>      /* edosd is now in the form needed for DRAMC[4:3]. */

Patch

Index: src/northbridge/intel/i440bx/raminit.c
===================================================================
--- src/northbridge/intel/i440bx/raminit.c	(revision 6460)
+++ src/northbridge/intel/i440bx/raminit.c	(working copy)
@@ -724,7 +724,7 @@ 
 	int i, dra, drb, col, width, value, rps, edosd, ecc, nbxecc;
 	u8 bpr; /* Top 8 bits of PGPOL */
 
-	edosd = 0;
+	edosd = 0x80;
 	rps = 0;
 	drb = 0;
 	bpr = 0;
@@ -748,7 +748,7 @@ 
 			}
 			PRINT_DEBUG("Found DIMM in slot %d\n", i);
 
-			if (edosd == 0x06) {
+			if ((edosd & 0x06) == 0x06) {
 				print_err("Mixing EDO/SDRAM unsupported!\n");
 				die("HALT\n");
 			}
@@ -782,6 +782,20 @@ 
 				ecc |= 0xc0;
 			}
 
+			/* If any installed DIMM is *not* registered, this system cannot be
+			 * configured for registered SDRAM.
+			 * By registered, only the address and control lines need to be, which
+			 * we can tell by reading SPD byte 21, bit 1.
+			 */
+			value = spd_read_byte(device, SPD_MODULE_ATTRIBUTES);
+			
+			PRINT_DEBUG("DIMM is ");
+			if ((value & 0x02) == 0) {
+				edosd &= 0x7f;
+				PRINT_DEBUG("not ");
+			}
+			PRINT_DEBUG("registered\n");
+			
 			/* Calculate page size in bits. */
 			value = ((1 << col) * width);
 
@@ -910,15 +924,20 @@ 
 	pci_write_config8(NB, NBXCFG + 3, nbxecc);
 	PRINT_DEBUG("NBXECC[31:24] has been set to 0x%02x\n", nbxecc);
 
-	/* Set DRAMC[4:3] to proper memory type (EDO/SDRAM).
-	 * TODO: Registered SDRAM support.
-	 */
-	edosd &= 0x07;
-	if (edosd & 0x02) {
-		edosd |= 0x00;
-	} else if (edosd & 0x04) {
-		edosd |= 0x08;
+	/* Set DRAMC[4:3] to proper memory type (EDO/SDRAM/Registered SDRAM). */
+
+	if ((edosd & 0x84) == 0x84) {
+		edosd = 0x10; // Registered SDRAM
+	} else {
+		// Clear [4:3] in case it's EDO.
+		edosd &= 0x07;
+//	} else if (edosd & 0x02) {
+//		edosd |= 0x00;
+		if (edosd & 0x04) {
+			edosd |= 0x08; // SDRAM
+		}
 	}
+	// Keep only [4:3].
 	edosd &= 0x18;
 
 	/* edosd is now in the form needed for DRAMC[4:3]. */