| Submitter | Marc Jones |
|---|---|
| Date | 2011-04-01 21:47:21 |
| Message ID | <AANLkTin8JBgqXHP=G2hvp_FFPY_6j+WRdPtkGHBPX4iy@mail.gmail.com> |
| Download | mbox | patch |
| Permalink | /patch/2844/ |
| State | Accepted |
| Headers | show |
Comments
Tested on the RS785E platform with Linux thanks Acked-by: Kerry she <Kerry.she@amd.com> -- Best Regards Kerry -----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Marc Jones Sent: Saturday, April 02, 2011 5:47 AM To: Rudolf Marek Cc: coreboot@coreboot.org Subject: Re: [coreboot] [patch] rs780 4GB memory issues On Fri, Apr 1, 2011 at 3:36 PM, Rudolf Marek <r.marek@assembler.cz> wrote: > Hi, > > How the patch actually works? It looks like it only prints TOM2 not > using it. Argh, .. and half the change doesn't help... *sigh* Thanks for catching that! Marc -- http://se-eng.com
Patch
Use TOM2 for highest sysmem setting for northbound memory routing (DMA). This fixes 4GB memory issues. Signed-off-by: Marc Jones <marcj303@gmail.com> Index: coreboot/src/southbridge/amd/rs780/gfx.c =================================================================== --- coreboot.orig/src/southbridge/amd/rs780/gfx.c 2011-04-01 13:36:27.122571002 -0600 +++ coreboot/src/southbridge/amd/rs780/gfx.c 2011-04-01 15:44:47.050571001 -0600 @@ -661,13 +661,15 @@ printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); - sysmem = rdmsr(0xc001001a); - printk(BIOS_DEBUG, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo); - /* The system top memory in 780. */ + sysmem = rdmsr(0xc001001a); + printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo); pci_write_config32(nb_dev, 0x90, sysmem.lo); - htiu_write_index(nb_dev, 0x30, 0); - htiu_write_index(nb_dev, 0x31, 0); + + sysmem = rdmsr(0xc001001D); + printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo); + htiu_write_index(nb_dev, 0x31, sysmem.hi); + htiu_write_index(nb_dev, 0x30, sysmem.lo | 1); /* Disable external GFX and enable internal GFX. */ l_dword = pci_read_config32(nb_dev, 0x8c);