Patchwork i945: improve get_top_of_ram()

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Submitter Sven Schnelle
Date 2011-04-09 11:31:23
Message ID <1302348683-13930-1-git-send-email-svens@stackframe.org>
Download mbox | patch
Permalink /patch/2860/
State Accepted
Headers show

Comments

Sven Schnelle - 2011-04-09 11:31:23
The current version doesn't honor TSEG, and fails to
report the correct top of RAM if IGD is disabled. This
is because it uses the BSM (base of stolen RAM) register.
In that case, we should use the TOLUD register.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
---
 src/northbridge/intel/i945/raminit.c |   30 +++++++++++++++++++++++++++---
 1 files changed, 27 insertions(+), 3 deletions(-)

Patch

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 8b7ffa1..c8bef11 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -3192,9 +3192,33 @@  void sdram_initialize(int boot_path, const u8 *spd_addresses)
 
 unsigned long get_top_of_ram(void)
 {
-	/* This will not work if TSEG is in place! */
-	u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+	u32 tom;
 
-	return (unsigned long) tom;
+	if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) {
+		/* IGD enabled, get top of Memory from BSM register */
+		tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+	} else {
+		tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
+	}
+
+	/* if TSEG enabled subtract size */
+	switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) {
+		case 0x01:
+			/* 1MB TSEG */
+			tom -= 0x10000;
+			break;
+		case 0x03:
+			/* 2MB TSEG */
+			tom -= 0x20000;
+			break;
+		case 0x05:
+			/* 8MB TSEG */
+			tom -= 0x80000;
+			break;
+		default:
+			/* TSEG either disabled or invalid */
+			break;
+	}
+	return (unsigned long)tom;
 }