From patchwork Mon Apr 18 23:06:49 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: drop some per-board cruft Date: Mon, 18 Apr 2011 23:06:49 -0000 From: Stefan Reinauer X-Patchwork-Id: 2886 Message-Id: <20110418230649.GA1275@coreboot.org> To: coreboot@coreboot.org See patch. Acked-by: Peter Stuge * Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value to unify calls to *_enable_usbdebug() * rename *_enable_usbdebug() to enable_usbdebug() * move enable_usbdebug() to generic romstage console init code and drop it from the individual romstage.c files. Something similar should happen to the uart init: * uart_init() can go into console.c right now * superio init should go into a function local_uart_init() defined in romstage.c and be called from console_init, too. Signed-off-by: Stefan Reinauer Index: src/southbridge/amd/sb600/Kconfig =================================================================== --- src/southbridge/amd/sb600/Kconfig (revision 6512) +++ src/southbridge/amd/sb600/Kconfig (working copy) @@ -36,6 +36,10 @@ hex default 0xe0 +config USBDEBUG_DEFAULT_PORT + int + default 0 + choice prompt "SATA Mode" default SATA_MODE_IDE Index: src/southbridge/amd/sb600/sb600.h =================================================================== --- src/southbridge/amd/sb600/sb600.h (revision 6512) +++ src/southbridge/amd/sb600/sb600.h (working copy) @@ -40,5 +40,5 @@ void sb600_lpc_port80(void); void sb600_pci_port80(void); -void sb600_enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int port); #endif /* SB600_H */ Index: src/southbridge/amd/sb600/enable_usbdebug.c =================================================================== --- src/southbridge/amd/sb600/enable_usbdebug.c (revision 6512) +++ src/southbridge/amd/sb600/enable_usbdebug.c (working copy) @@ -30,7 +30,7 @@ /* TODO: Allow changing the physical USB port used as Debug Port. */ } -void sb600_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ Index: src/southbridge/amd/sb700/sb700.h =================================================================== --- src/southbridge/amd/sb700/sb700.h (revision 6512) +++ src/southbridge/amd/sb700/sb700.h (working copy) @@ -75,5 +75,5 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -void sb7xx_51xx_enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int port); #endif /* SB700_H */ Index: src/southbridge/amd/sb700/enable_usbdebug.c =================================================================== --- src/southbridge/amd/sb700/enable_usbdebug.c (revision 6512) +++ src/southbridge/amd/sb700/enable_usbdebug.c (working copy) @@ -45,7 +45,7 @@ * This code currently only supports the first one, i.e., USB Debug devices * attached to physical USB ports belonging to the first EHCI device. */ -void sb7xx_51xx_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ Index: src/southbridge/amd/sb800/sb800.h =================================================================== --- src/southbridge/amd/sb800/sb800.h (revision 6512) +++ src/southbridge/amd/sb800/sb800.h (working copy) @@ -58,7 +58,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -void sb800_enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int port); #else void sb800_enable(device_t dev); void __attribute__((weak)) sb800_setup_sata_phys(struct device *dev); Index: src/southbridge/amd/sb800/enable_usbdebug.c =================================================================== --- src/southbridge/amd/sb800/enable_usbdebug.c (revision 6512) +++ src/southbridge/amd/sb800/enable_usbdebug.c (working copy) @@ -43,7 +43,7 @@ } -void sb800_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x13, 5), EHCI_BAR_INDEX, CONFIG_EHCI_BAR); Index: src/southbridge/nvidia/ck804/ck804.h =================================================================== --- src/southbridge/nvidia/ck804/ck804.h (revision 6512) +++ src/southbridge/nvidia/ck804/ck804.h (working copy) @@ -24,7 +24,7 @@ #include "chip.h" void ck804_enable(device_t dev); -void ck804_enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int port); extern struct pci_operations ck804_pci_ops; Index: src/southbridge/nvidia/ck804/enable_usbdebug.c =================================================================== --- src/southbridge/nvidia/ck804/enable_usbdebug.c (revision 6512) +++ src/southbridge/nvidia/ck804/enable_usbdebug.c (working copy) @@ -46,7 +46,7 @@ pci_write_config32(dev, 0x74, dword); } -void ck804_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ Index: src/southbridge/nvidia/mcp55/mcp55.h =================================================================== --- src/southbridge/nvidia/mcp55/mcp55.h (revision 6512) +++ src/southbridge/nvidia/mcp55/mcp55.h (working copy) @@ -35,7 +35,7 @@ #else #if !defined(__ROMCC__) void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); -void mcp55_enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int port); #endif #endif Index: src/southbridge/nvidia/mcp55/enable_usbdebug.c =================================================================== --- src/southbridge/nvidia/mcp55/enable_usbdebug.c (revision 6512) +++ src/southbridge/nvidia/mcp55/enable_usbdebug.c (working copy) @@ -40,7 +40,7 @@ pci_write_config32(dev, 0x74, dword); } -void mcp55_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ Index: src/southbridge/intel/i82801gx/i82801gx.h =================================================================== --- src/southbridge/intel/i82801gx/i82801gx.h (revision 6512) +++ src/southbridge/intel/i82801gx/i82801gx.h (working copy) @@ -46,7 +46,7 @@ void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); #endif -void i82801gx_enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int port); #endif #define MAINBOARD_POWER_OFF 0 Index: src/southbridge/intel/i82801gx/usb_debug.c =================================================================== --- src/southbridge/intel/i82801gx/usb_debug.c (revision 6512) +++ src/southbridge/intel/i82801gx/usb_debug.c (working copy) @@ -31,7 +31,7 @@ /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ } -void i82801gx_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { u32 dbgctl; device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ Index: src/southbridge/intel/i82801gx/Kconfig =================================================================== --- src/southbridge/intel/i82801gx/Kconfig (revision 6512) +++ src/southbridge/intel/i82801gx/Kconfig (working copy) @@ -24,11 +24,19 @@ select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT +if SOUTHBRIDGE_INTEL_I82801GX + config EHCI_BAR hex - default 0xfef00000 if SOUTHBRIDGE_INTEL_I82801GX + default 0xfef00000 config EHCI_DEBUG_OFFSET hex - default 0xa0 if SOUTHBRIDGE_INTEL_I82801GX + default 0xa0 +config USBDEBUG_DEFAULT_PORT + int + default 1 + +endif + Index: src/southbridge/intel/sch/usb_debug.c =================================================================== --- src/southbridge/intel/sch/usb_debug.c (revision 6512) +++ src/southbridge/intel/sch/usb_debug.c (working copy) @@ -30,7 +30,7 @@ /* Not needed, the southbridges hardcode physical USB port 1. */ } -void sch_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { u32 dbgctl; device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ Index: src/southbridge/sis/sis966/enable_usbdebug.c =================================================================== --- src/southbridge/sis/sis966/enable_usbdebug.c (revision 6512) +++ src/southbridge/sis/sis966/enable_usbdebug.c (working copy) @@ -42,7 +42,7 @@ pci_write_config32(dev, 0x74, dword); } -void sis966_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ Index: src/southbridge/sis/sis966/sis966.h =================================================================== --- src/southbridge/sis/sis966/sis966.h (revision 6512) +++ src/southbridge/sis/sis966/sis966.h (working copy) @@ -40,7 +40,7 @@ #endif #if defined(__PRE_RAM__) && !defined(__ROMCC__) -void sis966_enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int port); #endif #endif /* SIS966_H */ Index: src/mainboard/asrock/939a785gmh/romstage.c =================================================================== --- src/mainboard/asrock/939a785gmh/romstage.c (revision 6512) +++ src/mainboard/asrock/939a785gmh/romstage.c (working copy) @@ -160,11 +160,6 @@ w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/getac/p470/romstage.c =================================================================== --- src/mainboard/getac/p470/romstage.c (revision 6512) +++ src/mainboard/getac/p470/romstage.c (working copy) @@ -288,10 +288,6 @@ /* Set up the console */ uart_init(); -#if CONFIG_USBDEBUG - i82801gx_enable_usbdebug(1); - early_usbdebug_init(); -#endif console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/supermicro/h8scm_fam10/romstage.c =================================================================== --- src/mainboard/supermicro/h8scm_fam10/romstage.c (revision 6512) +++ src/mainboard/supermicro/h8scm_fam10/romstage.c (working copy) @@ -125,12 +125,7 @@ sb7xx_51xx_disable_wideio(0); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Index: src/mainboard/kontron/986lcd-m/romstage.c =================================================================== --- src/mainboard/kontron/986lcd-m/romstage.c (revision 6512) +++ src/mainboard/kontron/986lcd-m/romstage.c (working copy) @@ -337,11 +337,6 @@ /* Set up the console */ uart_init(); -#if CONFIG_USBDEBUG - i82801gx_enable_usbdebug(1); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/kontron/kt690/romstage.c =================================================================== --- src/mainboard/kontron/kt690/romstage.c (revision 6512) +++ src/mainboard/kontron/kt690/romstage.c (working copy) @@ -96,11 +96,6 @@ w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb600_enable_usbdebug(0); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/gigabyte/m57sli/romstage.c =================================================================== --- src/mainboard/gigabyte/m57sli/romstage.c (revision 6512) +++ src/mainboard/gigabyte/m57sli/romstage.c (working copy) @@ -150,10 +150,6 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); Index: src/mainboard/gigabyte/ma78gm/romstage.c =================================================================== --- src/mainboard/gigabyte/ma78gm/romstage.c (revision 6512) +++ src/mainboard/gigabyte/ma78gm/romstage.c (working copy) @@ -106,13 +106,7 @@ it8718f_disable_reboot(); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); /* Halt if there was a built in self test failure */ report_bist_failure(bist); Index: src/mainboard/gigabyte/ga_2761gxdk/romstage.c =================================================================== --- src/mainboard/gigabyte/ga_2761gxdk/romstage.c (revision 6512) +++ src/mainboard/gigabyte/ga_2761gxdk/romstage.c (working copy) @@ -147,10 +147,6 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if CONFIG_USBDEBUG - sis966_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); Index: src/mainboard/gigabyte/ma785gmt/romstage.c =================================================================== --- src/mainboard/gigabyte/ma785gmt/romstage.c (revision 6512) +++ src/mainboard/gigabyte/ma785gmt/romstage.c (working copy) @@ -102,11 +102,6 @@ it8718f_disable_reboot(); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); printk(BIOS_DEBUG, "\n"); Index: src/mainboard/amd/mahogany/romstage.c =================================================================== --- src/mainboard/amd/mahogany/romstage.c (revision 6512) +++ src/mainboard/amd/mahogany/romstage.c (working copy) @@ -93,11 +93,6 @@ it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/amd/pistachio/romstage.c =================================================================== --- src/mainboard/amd/pistachio/romstage.c (revision 6512) +++ src/mainboard/amd/pistachio/romstage.c (working copy) @@ -91,11 +91,6 @@ * and it doesn't require any special setup. */ uart_init(); -#if CONFIG_USBDEBUG - sb600_enable_usbdebug(0); - early_usbdebug_init(); -#endif - console_init(); post_code(0x03); Index: src/mainboard/amd/dbm690t/romstage.c =================================================================== --- src/mainboard/amd/dbm690t/romstage.c (revision 6512) +++ src/mainboard/amd/dbm690t/romstage.c (working copy) @@ -94,11 +94,6 @@ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb600_enable_usbdebug(0); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/amd/mahogany_fam10/romstage.c =================================================================== --- src/mainboard/amd/mahogany_fam10/romstage.c (revision 6512) +++ src/mainboard/amd/mahogany_fam10/romstage.c (working copy) @@ -106,13 +106,7 @@ it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Index: src/mainboard/amd/tilapia_fam10/romstage.c =================================================================== --- src/mainboard/amd/tilapia_fam10/romstage.c (revision 6512) +++ src/mainboard/amd/tilapia_fam10/romstage.c (working copy) @@ -105,13 +105,7 @@ it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Index: src/mainboard/amd/bimini_fam10/romstage.c =================================================================== --- src/mainboard/amd/bimini_fam10/romstage.c (revision 6512) +++ src/mainboard/amd/bimini_fam10/romstage.c (working copy) @@ -110,12 +110,7 @@ sb800_lpc_init(); uart_init(); -#if CONFIG_USBDEBUG - sb800_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Index: src/mainboard/lenovo/x60/romstage.c =================================================================== --- src/mainboard/lenovo/x60/romstage.c (revision 6512) +++ src/mainboard/lenovo/x60/romstage.c (working copy) @@ -242,11 +242,6 @@ uart_init(); } -#if CONFIG_USBDEBUG - i82801gx_enable_usbdebug(1); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/iei/kino-780am2-fam10/romstage.c =================================================================== --- src/mainboard/iei/kino-780am2-fam10/romstage.c (revision 6512) +++ src/mainboard/iei/kino-780am2-fam10/romstage.c (working copy) @@ -107,13 +107,7 @@ f71859_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Index: src/mainboard/tyan/s2912/romstage.c =================================================================== --- src/mainboard/tyan/s2912/romstage.c (revision 6512) +++ src/mainboard/tyan/s2912/romstage.c (working copy) @@ -136,10 +136,6 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); Index: src/mainboard/tyan/s2912_fam10/romstage.c =================================================================== --- src/mainboard/tyan/s2912_fam10/romstage.c (revision 6512) +++ src/mainboard/tyan/s2912_fam10/romstage.c (working copy) @@ -138,16 +138,10 @@ w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - printk(BIOS_DEBUG, "\n"); /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); Index: src/mainboard/ibase/mb899/romstage.c =================================================================== --- src/mainboard/ibase/mb899/romstage.c (revision 6512) +++ src/mainboard/ibase/mb899/romstage.c (working copy) @@ -239,11 +239,6 @@ /* Set up the console */ uart_init(); -#if CONFIG_USBDEBUG - i82801gx_enable_usbdebug(1); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/roda/rk886ex/romstage.c =================================================================== --- src/mainboard/roda/rk886ex/romstage.c (revision 6512) +++ src/mainboard/roda/rk886ex/romstage.c (working copy) @@ -272,11 +272,6 @@ /* Set up the console */ uart_init(); -#if CONFIG_USBDEBUG - i82801gx_enable_usbdebug(1); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/msi/ms9652_fam10/romstage.c =================================================================== --- src/mainboard/msi/ms9652_fam10/romstage.c (revision 6512) +++ src/mainboard/msi/ms9652_fam10/romstage.c (working copy) @@ -138,16 +138,10 @@ w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - printk(BIOS_DEBUG, "\n"); /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); Index: src/mainboard/msi/ms7260/romstage.c =================================================================== --- src/mainboard/msi/ms7260/romstage.c (revision 6512) +++ src/mainboard/msi/ms7260/romstage.c (working copy) @@ -139,10 +139,6 @@ setup_mb_resource_map(); uart_init(); report_bist_failure(bist); /* Halt upon BIST failure. */ -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); Index: src/mainboard/jetway/pa78vm5/romstage.c =================================================================== --- src/mainboard/jetway/pa78vm5/romstage.c (revision 6512) +++ src/mainboard/jetway/pa78vm5/romstage.c (working copy) @@ -112,13 +112,7 @@ f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Index: src/mainboard/technexion/tim8690/romstage.c =================================================================== --- src/mainboard/technexion/tim8690/romstage.c (revision 6512) +++ src/mainboard/technexion/tim8690/romstage.c (working copy) @@ -95,11 +95,6 @@ it8712f_kill_watchdog(); uart_init(); -#if CONFIG_USBDEBUG - sb600_enable_usbdebug(0); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/technexion/tim5690/romstage.c =================================================================== --- src/mainboard/technexion/tim5690/romstage.c (revision 6512) +++ src/mainboard/technexion/tim5690/romstage.c (working copy) @@ -100,11 +100,6 @@ it8712f_kill_watchdog(); uart_init(); -#if CONFIG_USBDEBUG - sb600_enable_usbdebug(0); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/nvidia/l1_2pvv/romstage.c =================================================================== --- src/mainboard/nvidia/l1_2pvv/romstage.c (revision 6512) +++ src/mainboard/nvidia/l1_2pvv/romstage.c (working copy) @@ -140,10 +140,6 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); Index: src/mainboard/intel/d945gclf/romstage.c =================================================================== --- src/mainboard/intel/d945gclf/romstage.c (revision 6512) +++ src/mainboard/intel/d945gclf/romstage.c (working copy) @@ -200,11 +200,6 @@ /* Set up the console */ uart_init(); -#if CONFIG_USBDEBUG - i82801gx_enable_usbdebug(1); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/asus/m4a785-m/romstage.c =================================================================== --- src/mainboard/asus/m4a785-m/romstage.c (revision 6512) +++ src/mainboard/asus/m4a785-m/romstage.c (working copy) @@ -106,13 +106,7 @@ it8712f_kill_watchdog(); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Index: src/mainboard/asus/m4a78-em/romstage.c =================================================================== --- src/mainboard/asus/m4a78-em/romstage.c (revision 6512) +++ src/mainboard/asus/m4a78-em/romstage.c (working copy) @@ -106,13 +106,7 @@ it8712f_kill_watchdog(); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Index: src/mainboard/asus/m2n-e/romstage.c =================================================================== --- src/mainboard/asus/m2n-e/romstage.c (revision 6512) +++ src/mainboard/asus/m2n-e/romstage.c (working copy) @@ -123,10 +123,6 @@ setup_mb_resource_map(); uart_init(); report_bist_failure(bist); -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1); Index: src/console/console.c =================================================================== --- src/console/console.c (revision 6512) +++ src/console/console.c (working copy) @@ -95,6 +95,10 @@ void console_init(void) { +#if CONFIG_USBDEBUG + enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); + early_usbdebug_init(); +#endif #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); #endif