From patchwork Tue Apr 19 19:47:15 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [1/4] pci1x2x: use devicetree register configuration Date: Tue, 19 Apr 2011 19:47:15 -0000 From: Sven Schnelle X-Patchwork-Id: 2889 Message-Id: <1303242438-13852-2-git-send-email-svens@stackframe.org> To: coreboot@coreboot.org Cc: svens@stackframe.org Signed-off-by: Sven Schnelle Acked-by: Stefan Reinauer --- src/mainboard/nokia/ip530/Kconfig | 25 --------------------- src/mainboard/nokia/ip530/devicetree.cb | 9 +++++++ src/southbridge/ti/pci1x2x/pci1x2x.c | 36 +++++++++++++----------------- 3 files changed, 25 insertions(+), 45 deletions(-) diff --git a/src/mainboard/nokia/ip530/Kconfig b/src/mainboard/nokia/ip530/Kconfig index 0eac00a..b5abb89 100644 --- a/src/mainboard/nokia/ip530/Kconfig +++ b/src/mainboard/nokia/ip530/Kconfig @@ -45,29 +45,4 @@ config IRQ_SLOT_COUNT int default 22 -## Configuration for the PCMCIA-Cardbus controller. -config TI_PCMCIA_CARDBUS_CMDR - hex - default 0x0107 - -config TI_PCMCIA_CARDBUS_CLSR - hex - default 0x00 - -config TI_PCMCIA_CARDBUS_CLTR - hex - default 0x40 - -config TI_PCMCIA_CARDBUS_BCR - hex - default 0x07C0 - -config TI_PCMCIA_CARDBUS_SCR - hex - default 0x08449060 - -config TI_PCMCIA_CARDBUS_MRR - hex - default 0x00007522 - endif # BOARD_NOKIA_IP530 diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb index 3cfbc8f..54ebb1a 100644 --- a/src/mainboard/nokia/ip530/devicetree.cb +++ b/src/mainboard/nokia/ip530/devicetree.cb @@ -28,6 +28,15 @@ chip northbridge/intel/i440bx # Northbridge device pci 0.0 on end # Host bridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge + device pci f.0 on + chip southbridge/ti/pci1x2x + device pci 00.0 on + + end + register "scr" = "0x08449060" + register "mrr" = "0x00007522" + end + end device pci 7.0 on # ISA bridge chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787) device pnp 3f0.0 off end # Floppy (No connector) diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index 63a0646..121b9ef 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -23,28 +23,20 @@ #include #include #include - -#if (!defined(CONFIG_TI_PCMCIA_CARDBUS_CMDR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_CLSR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_CLTR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_BCR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_SCR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_MRR)) -#error "you must supply these values in your mainboard-specific Kconfig file" -#endif +#include "chip.h" static void ti_pci1x2y_init(struct device *dev) { + printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n"); + struct southbridge_ti_pci1x2x_config *conf = dev->chip_info; - /* Command (offset 04) */ - pci_write_config16(dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR); /* Cache Line Size (offset 0x0C) */ - pci_write_config8(dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR); + pci_write_config8(dev, 0x0C, conf->clsr); /* CardBus latency timer (offset 0x1B) */ - pci_write_config8(dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR); + pci_write_config8(dev, 0x1B, conf->cltr); /* Bridge control (offset 0x3E) */ - pci_write_config16(dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR); + pci_write_config16(dev, 0x3E, conf->bcr); /* * Enable change sub-vendor ID. Clear the bit 5 to enable to write * to the sub-vendor/device ids at 40 and 42. @@ -53,14 +45,14 @@ static void ti_pci1x2y_init(struct device *dev) pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA); /* Now write the correct value for SCR. */ /* System control (offset 0x80) */ - pci_write_config32(dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR); + pci_write_config32(dev, 0x80, conf->scr); /* Multifunction routing */ - pci_write_config32(dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR); + pci_write_config32(dev, 0x8C, conf->mrr); /* Set the device control register (0x92) accordingly. */ pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02); } -static struct device_operations ti_pci1x2y_ops = { +struct device_operations southbridge_ti_pci1x2x_pciops = { .read_resources = NULL, //pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -69,19 +61,23 @@ static struct device_operations ti_pci1x2y_ops = { }; static const struct pci_driver ti_pci1225_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1225, }; static const struct pci_driver ti_pci1420_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1420, }; static const struct pci_driver ti_pci1520_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1520, }; + +struct chip_operations southbridge_ti_pci1x2x_ops = { + CHIP_NAME("TI PCI1x2x Cardbus controller") +};