Patchwork [2/4] compile sb800 code without agesav5

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Submitter She, Kerry
Date 2011-04-25 11:57:58
Message ID <F53A09371FB723428826B442A4B20A4105DA21D8@sbjgexmb1.amd.com>
Download mbox | patch
Permalink /patch/2914/
State New
Headers show

Comments

She, Kerry - 2011-04-25 11:57:58
Hello Stefan

The sb800 cimx code originally has its own lib function code,
But these files was removed in the current tree. 
As for now sb800 cimx code share the Agesa v5 lib function code,
but this sharing cause it is not possible to use sb800 cimx wrapper without compile Agesa v5 lib files.

This patch implement the lib function needed by sb800 cimx,
So we can use the sb800 cimx wrapper and Agesa v5 wrapper independently.  

Thanks

--
kerry

> -----Original Message-----

> From: Stefan Reinauer [mailto:stefan.reinauer@coreboot.org]

> Sent: Saturday, April 23, 2011 3:58 AM

> To: She, Kerry

> Cc: coreboot@coreboot.org

> Subject: Re: [coreboot] [Patch 2/4] compile sb800 code without agesav5

> 

> * She, Kerry <Kerry.She@amd.com> [110422 05:12]:

> > Signed-off-by: Kerry She <Kerry.she@amd.com>

> >

> > SB800 CIMX code can share the AGESA V5 lib code,

> > some platform only use sb800 cimx code, not use AGESA v5 code,

> > compile the sb800 cimx and AGESA v5 lib code.

> >

> > Signed-off-by: Kerry She <Kerry.she@amd.com>

> >

> > Index: Makefile.inc

> > ===================================================================

> > --- Makefile.inc        (revision 6481)

> > +++ Makefile.inc        (working copy)

> > @@ -110,7 +110,9 @@

> >  CFLAGS += -Werror

> >  endif

> >  ifneq ($(CONFIG_AMD_AGESA),y)

> > -CFLAGS += -nostdinc

> > + ifneq ($(CONFIG_AMD_CIMX_SB800),y)

> > +  CFLAGS += -nostdinc

> > + endif

> >  endif

> >  CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer

> >

> 

> Why is that needed. Can we instead fix the code, please?

>
this patch switch to use the sb800 old lib code.

Patch

Index: src/vendorcode/amd/cimx/lib/amdlib32.h
===================================================================
--- src/vendorcode/amd/cimx/lib/amdlib32.h	(revision 0)
+++ src/vendorcode/amd/cimx/lib/amdlib32.h	(revision 0)
@@ -0,0 +1,16 @@ 
+#ifndef _AMDLIB32_H_
+#define _AMDLIB32_H_
+
+#include "cbtypes.h"
+#include "Amd.h"
+
+UINT8 ReadIo8 (IN UINT16 port);
+UINT16 ReadIo16 (IN UINT16 port);
+UINT32 ReadIo32 (IN UINT16 port);
+VOID WriteIo8 (IN UINT16 port, IN UINT8 value);
+VOID WriteIo16 (IN UINT16 port, IN UINT16 value);
+VOID WriteIo32 (IN UINT16 port, IN UINT32 value);
+UINT64 ReadTSC(VOID);
+VOID CpuidRead(IN UINT32 op, IN OUT CPUID_DATA* Data);
+UINT8 ReadNumberOfCpuCores(VOID);
+#endif //_AMDLIB32_H_
Index: src/vendorcode/amd/cimx/lib/Makefile.inc
===================================================================
--- src/vendorcode/amd/cimx/lib/Makefile.inc	(revision 0)
+++ src/vendorcode/amd/cimx/lib/Makefile.inc	(revision 0)
@@ -0,0 +1,3 @@ 
+
+romstage-y += amdlib32.c
+ramstage-y += amdlib32.c
Index: src/vendorcode/amd/cimx/lib/amdlib32.c
===================================================================
--- src/vendorcode/amd/cimx/lib/amdlib32.c	(revision 0)
+++ src/vendorcode/amd/cimx/lib/amdlib32.c	(revision 0)
@@ -0,0 +1,84 @@ 
+#include "amdlib32.h"
+
+UINT8 ReadIo8 (IN UINT16 port)
+{
+	UINT8 value;
+	__asm__ __volatile__ ("inb %w1, %b0" : "=a"(value) : "Nd" (port));
+	return value;
+}
+
+UINT16 ReadIo16 (IN UINT16 port)
+{
+        UINT16 value;
+        __asm__ __volatile__ ("inw %w1, %w0" : "=a"(value) : "Nd" (port));
+        return value;
+}
+
+UINT32 ReadIo32 (IN UINT16 port)
+{
+        UINT32 value;
+        __asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port));
+        return value;
+}
+
+VOID WriteIo8 (IN UINT16 port, IN UINT8 value)
+{
+        __asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port));
+}
+
+VOID WriteIo16 (IN UINT16 port, IN UINT16 value)
+{
+        __asm__ __volatile__ ("outw %w0, %w1" : : "a" (value), "Nd" (port));
+}
+
+VOID WriteIo32 (IN UINT16 port, IN UINT32 value)
+{
+        __asm__ __volatile__ ("outl %0, %w1" : : "a" (value), "Nd" (port));
+}
+
+UINT64 ReadTSC(VOID)
+{
+	struct tsc_struct {
+		unsigned lo;
+		unsigned hi;
+	} res;
+	UINT64 ret;
+
+	__asm__ __volatile__ (
+			"rdtsc" 
+			: "=a" (res.lo), "=d"(res.hi) /* outputs */
+			);
+	ret = res.hi;
+	ret <<= 32;
+	ret |= res.lo;
+	return ret;
+}
+
+VOID CpuidRead(IN UINT32 op, IN OUT CPUID_DATA* Data)
+{
+        asm volatile(
+                "cpuid"
+                : "=a" (Data->EAX_Reg),
+                  "=b" (Data->EBX_Reg),
+                  "=c" (Data->ECX_Reg),
+                  "=d" (Data->EDX_Reg)
+                : "0" (op));
+}
+
+static inline unsigned int cpuid_ecx(unsigned int op)
+{
+        unsigned int eax, ecx;
+
+        __asm__("cpuid"
+                : "=a" (eax), "=c" (ecx)
+                : "0" (op)
+                : "ebx", "edx" );
+        return ecx;
+}
+
+//static inline unsigned get_core_num(void)
+UINT8 ReadNumberOfCpuCores(VOID)
+{
+        return (cpuid_ecx(0x80000008) & 0xff);
+}
+
Index: src/mainboard/advansus/a785e-i/Makefile.inc
===================================================================
--- src/mainboard/advansus/a785e-i/Makefile.inc	(revision 1168)
+++ src/mainboard/advansus/a785e-i/Makefile.inc	(working copy)
@@ -5,17 +5,14 @@ 
 ramstage-y += pmio.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
 
+subdirs-y += ../../../../src/vendorcode/amd/cimx/lib
 #SB800 CIMx share AGESA V5 lib code
 ifneq ($(CONFIG_AMD_AGESA),y)