===================================================================
@@ -1853,11 +1856,150 @@
+
+
+static int wait_uc_writebuf_empty(uint16_t port)
+{
+ int count;
+
+ for (count = 0; count < 50; count++)
+ {
+ /* quit if OBF bit clear */
+ if (!(INB(port + 4) & 2))
+ {
+ msg_pinfo("EC write buffer is already empty.\n");
+ return 0;
+ }
+ usleep(10000);
+ }
+ msg_perr("wait_uc_writebuf_empty returned false or EC write buffer not empty.\n");
+ return -1;
+}
+
+static int uc_send_command(uint16_t port, uint8_t command)
+{
+ if (wait_uc_writebuf_empty(port) != 0)
+ return -1;
+ OUTB(command, port + 4);
+ return 0;
+}
+
+static int uc_send_data(uint16_t port, uint8_t command)
+{
+ if (wait_uc_writebuf_empty(port) != 0)
+ return -1;
+ OUTB(command, port);
+ return 0;
+}
+
+static int compal_os_takeover_fan(void)
+{
+ if(uc_send_command(0x60, 0x59) != 0) // system state notification
+ {
+ msg_perr("Unable to send System State Notification.\n");
+ return -1;
+ }
+
+ if(uc_send_data(0x60, 0xA8) != 0) // disable EC fan control
+ {
+ msg_perr("Unable to disable fan control by the EC.\n");
+ return -1;
+ }
+ if(uc_send_command(0x60, 0x49) != 0) // thermal state notification
+ {
+ msg_perr("Unable to send Thermal State Notification.\n");
+ return -1;
+ }
+ if(uc_send_data(0x60, 0xA2) != 0) // set fans to level 2
+ {
+ msg_perr("Unable to set fans to high speed.\n");
+ return -1;
+ }
+ return 0;
+}
+
+static int compal_pc87591_flash_enable(void)
+{
+ int i;
+ unsigned int flashcontrolbase;
+
+ /* select logical device 0xf: shared BIOS and flash control */
+ sio_write(0x4C, 0x7, 0xF);
+ sio_write(0x4C, 0x30, 0x1); /* activate processor access */
+
+ /* get I/O base address */
+ flashcontrolbase = sio_read(0x4C, 0x61) | (sio_read(0x4C, 0x60) << 8);
+ msg_pinfo("flash control base address is 0x%x\n", flashcontrolbase);
+ for(i = 0; i < 16; i++)
+ OUTB(i * 0x10, flashcontrolbase+8); /* remove protection of flash segment i */
+
+ if(uc_send_command(0x60, 0x59) != 0) // system state notification
+ {
+ msg_perr("Unable to send System State Notification.\n");
+ return -1;
+ }
+
+ if(uc_send_data(0x60, 0xF2) != 0) // enter flash mode
+ {
+ msg_perr("Unable to put the EC into flash mode.\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static int intel_ich_gpio25_lower(void)
+{
+ return intel_ich_gpio_set(25, 0);
+}
+
+static void toshiba_flashmode_exit(void * cmdptr)
+{
+ if(uc_send_command(0x60, 0x49) != 0) // thermal state notification to get it out of flash mode
+ {
+ msg_perr("Unable to send Thermal State Notification.\n");
+ return;
+ }
+
+ if(uc_send_data(0x60, 0xA2) != 0) // set fans to level 2 again
+ {
+ msg_perr("Unable to set fans back to level 1.\n");
+ return;
+ }
+}
+
+static int board_toshiba_satellite_s520(void)
+{
+ /* Original ASM Code Copyright (C) 2004 Toshiba and/or Compal. */
+ if(compal_os_takeover_fan() != 0)
+ {
+ msg_perr("compal_os_takeover_fan() is not returning 0.\n");
+ return -1;
+ }
+
+ if(compal_pc87591_flash_enable() != 0)
+ {
+ msg_perr("compal_pc87591_flash_enable() is not returning 0.\n");
+ return -1;
+ }
+
+
+ if (intel_ich_gpio25_lower() != 0)
+ {
+ msg_perr("Unable to lower GPIO 25.\n");
+ return -1;
+ }
+
+ register_shutdown(toshiba_flashmode_exit, NULL);
+ buses_supported = CHIP_BUSTYPE_PARALLEL;
+ return 0;
+}
+
/*
* Below is the list of boards which need a special "board enable" code in
* flashrom before their ROM chip can be accessed/written to.
@@ -1900,112 +2042,113 @@
/* Please keep this list alphabetically ordered by vendor/board name. */
const struct board_pciid_enable board_pciid_enables[] = {
/* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */
#if defined(__i386__) || defined(__x86_64__)
{0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
{0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower},