| Submitter | Scott |
|---|---|
| Date | 2011-04-30 09:10:59 |
| Message ID | <B0FDAE3158B74F6497F657AD6D0408C4@m3a78> |
| Download | mbox | patch |
| Permalink | /patch/2931/ |
| State | Accepted |
| Commit | r6580 |
| Headers | show |
Comments
On Sat, Apr 30, 2011 at 3:10 AM, Scott Duplichan <scott@notabs.org> wrote: > The attached changes for the AMD Persimmon board improve OS support and reduce boot time. > DOS boot from SSD drive is 640 ms. Windows 7, Windows XP, and linux can install from > DVD and boot from hard disk. > > Signed-off-by: Scott Duplichan <scott@notabs.org> > > Thanks, > Scott H Scott, Thanks for all the patches. I missed this while I was on the road. I will start reviewing these over the next few days. Maybe we can get some others to help review and test too. Marc
On Sat, Apr 30, 2011 at 3:10 AM, Scott Duplichan <scott@notabs.org> wrote: > The attached changes for the AMD Persimmon board improve OS support and reduce boot time. > DOS boot from SSD drive is 640 ms. Windows 7, Windows XP, and linux can install from > DVD and boot from hard disk. > > Signed-off-by: Scott Duplichan <scott@notabs.org> Hi Scott, I'm acking and committing all except the LTO patch, which should wait for the crossgcc changes for gcc4.6. i only made a minor tweak to the AHCI patch to add a #define for the PCI DID. 02-26 - Acked-by: Marc Jones <marcj303@gmail.com> r6571 - r6594 Marc
Marc Jones wrote: ]Hi Scott, ] ]I'm acking and committing all except the LTO patch, which should wait ]for the crossgcc changes for gcc4.6. i only made a minor tweak to the ]AHCI patch to add a #define for the PCI DID. Thanks Marc. I noticed the PCI ID also, how embarrassing! I will test everything and try to make some of the changes suggested by Peter and Stefan. After that, I need to do the same for asrock e350m1. Thanks, Scott
Patch
Index: src/southbridge/amd/cimx_wrapper/sb800/late.c =================================================================== --- src/southbridge/amd/cimx_wrapper/sb800/late.c (revision 6551) +++ src/southbridge/amd/cimx_wrapper/sb800/late.c (working copy) @@ -352,6 +352,25 @@ break; case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ + { + u8 byte; + u32 ioapic_base; + + printk(BIOS_INFO, "sm_init().\n"); + ioapic_base = 0xFEC00000; + clear_ioapic(ioapic_base); + /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ + #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) + /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ + setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); + #elif (CONFIG_APIC_ID_OFFSET > 0) + /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ + setup_ioapic(ioapic_base, 0); + #else + #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" + #endif + } + break; case (0x14 << 3) | 1: /* 0:14:1 IDE */