From patchwork Sat Apr 30 09:10:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: AMD Persimmon update Date: Sat, 30 Apr 2011 09:10:59 -0000 From: Scott X-Patchwork-Id: 2931 Message-Id: To: The attached changes for the AMD Persimmon board improve OS support and reduce boot time. DOS boot from SSD drive is 640 ms. Windows 7, Windows XP, and linux can install from DVD and boot from hard disk. Signed-off-by: Scott Duplichan Thanks, Scott Build device paths for AP cores so that coreboot will report them to the OS. Signed-off-by: Scott Duplichan Enable 33 MHz fast mode SPI read early to reduce boot time. Signed-off-by: Scott Duplichan Switch processor cores to pstate 0 early to reduce boot time. Signed-off-by: Scott Duplichan Enable SPI cacheline prefetch early to reduce boot time. Signed-off-by: Scott Duplichan Move SB800 clock init earlier to fix problem where initial serial port output is garbled. Signed-off-by: Scott Duplichan 1) Make fadt revision match its length. Solves Windows 7 checked build assert. Signed-off-by: Scott Duplichan 1) Declare RTC as not PIIX4 compatible to match AMD hardware. Signed-off-by: Scott Duplichan Declare legacy video frame buffer so that Windows generic VGA driver will work. Signed-off-by: Scott Duplichan Remove some non-essential agesa options to reduce boot time. Signed-off-by: Scott Duplichan Fix memory allocation problem in amdInitLate. Disabled until further debug. Signed-off-by: Scott Duplichan Enable rom cache early to reduce boot time. Signed-off-by: Scott Duplichan Update gpp port configuration. Signed-off-by: Scott Duplichan 1) Remove unused kconfig options. 2) Correct UMA graphics PCI device ID. Signed-off-by: Scott Duplichan Cosmetic changes. Signed-off-by: Scott Duplichan Add kconfig option for gcc link time optimization (-flto). Reguires gcc 4.6.0 or later. Signed-off-by: Scott Duplichan 1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization. 2) Remove coreboot variable MTRR initialization because AMD reference code handles it. Signed-off-by: Scott Duplichan Correct the number of MCA error reporting banks cleared. Signed-off-by: Scott Duplichan 1) Set I/O APIC ID according to BKDG recommendation 2) Correct I/O APIC ID reported by mptable Signed-off-by: Scott Duplichan 1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support. 2) Extend PCI MMIO limit from dfffffff to fecfffff. 3) Add AMD recommended non-posted mapping for SB800 legacy devices. Signed-off-by: Scott Duplichan Size mmconf according to CONFIG_MMCONF_BUS_NUMBER. Signed-off-by: Scott Duplichan Match DIMM SPD addressing to implemented slots. Signed-off-by: Scott Duplichan Configure CIMx to use 33 MHz fast mode for SPD read. Signed-off-by: Scott Duplichan Fix ACPI shutdown function by removing reliance on SMI. Signed-off-by: Scott Duplichan Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR. Signed-off-by: Scott Duplichan Enable AHCI mode and hide IDE controller to reduce boot time. Note: enable AHCI in seabios and apply seabios patch: http://www.mail-archive.com/seabios@seabios.org/msg00437.html Signed-off-by: Scott Duplichan Program the I/O APIC ID. Signed-off-by: Scott Duplichan Index: src/southbridge/amd/cimx_wrapper/sb800/late.c =================================================================== --- src/southbridge/amd/cimx_wrapper/sb800/late.c (revision 6551) +++ src/southbridge/amd/cimx_wrapper/sb800/late.c (working copy) @@ -352,6 +352,25 @@ break; case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ + { + u8 byte; + u32 ioapic_base; + + printk(BIOS_INFO, "sm_init().\n"); + ioapic_base = 0xFEC00000; + clear_ioapic(ioapic_base); + /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ + #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) + /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ + setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); + #elif (CONFIG_APIC_ID_OFFSET > 0) + /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ + setup_ioapic(ioapic_base, 0); + #else + #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" + #endif + } + break; case (0x14 << 3) | 1: /* 0:14:1 IDE */