Patchwork here's the now completely fixed patch.

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Submitter Brandon Dowdy
Date 2011-05-01 16:11:27
Message ID <BANLkTi=U5y1ABO0sSdsoRrCPouvkd0CVwA@mail.gmail.com>
Download mbox | patch
Permalink /patch/2932/
State Bitrotted
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Comments

Brandon Dowdy - 2011-05-01 16:11:27
I think this patch is fixed now.

Patch

Index: board_enable.c
===================================================================
--- board_enable.c	(revision 1288)
+++ board_enable.c	(working copy)
@@ -24,10 +24,13 @@ 
  * Contains the board specific flash enables.
  */
 
+#include <unistd.h>
 #include <string.h>
 #include "flash.h"
 #include "programmer.h"
 
+int usleep(useconds_t usec);
+
 #if defined(__i386__) || defined(__x86_64__)
 /*
  * Helper functions for many Winbond Super I/Os of the W836xx range.
@@ -145,7 +148,7 @@ 
 struct winbond_port {
 	const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
 	uint8_t ldn;		/* LDN this GPIO register is located in */
-	uint8_t enable_bit;	/* bit in 0x30 of that LDN to enable 
+        uint8_t enable_bit;     /* bit in 0x30 of that LDN to enable
 	                           the GPIO port */
 	uint8_t base;		/* base register in that LDN for the port */
 };
@@ -873,7 +876,7 @@ 
 	case 0x0364: /* MCP55 */
 		/* find SMBus controller on *this* southbridge */
 		/* The infamous Tyan S2915-E has two south bridges; they are
-		   easily told apart from each other by the class of the 
+                   easily told apart from each other by the class of the
 		   LPC bridge, but have the same SMBus bridge IDs */
 		if (dev->func != 0) {
 			msg_perr("MCP LPC bridge at unexpected function"
@@ -1858,6 +1861,145 @@ 
 
 #endif
 
+
+
+static int wait_uc_writebuf_empty(uint16_t port)
+{
+    int count;
+
+    for (count = 0; count < 50; count++)
+    {
+        /* quit if OBF bit clear */
+        if (!(INB(port + 4) & 2))
+        { 
+            msg_pinfo("EC write buffer is already empty.\n");
+            return 0;
+        }
+        usleep(10000);
+    }
+    msg_perr("wait_uc_writebuf_empty returned false or EC write buffer not empty.\n");
+    return -1;
+}
+
+static int uc_send_command(uint16_t port, uint8_t command)
+{
+       if (wait_uc_writebuf_empty(port) != 0)
+               return -1;
+       OUTB(command, port + 4);
+       return 0;
+}
+
+static int uc_send_data(uint16_t port, uint8_t command)
+{
+       if (wait_uc_writebuf_empty(port) != 0)
+               return -1;
+       OUTB(command, port);
+       return 0;
+}
+
+static int compal_os_takeover_fan(void) 
+{
+    if(uc_send_command(0x60, 0x59) != 0) // system state notification
+    {
+        msg_perr("Unable to send System State Notification.\n");
+        return -1;
+    }
+
+    if(uc_send_data(0x60, 0xA8) != 0) // disable EC fan control
+    {
+        msg_perr("Unable to disable fan control by the EC.\n");
+        return -1;
+    }
+    if(uc_send_command(0x60, 0x49) != 0) // thermal state notification
+    {
+        msg_perr("Unable to send Thermal State Notification.\n");
+        return -1;
+    }
+    if(uc_send_data(0x60, 0xA2) != 0) // set fans to level 2
+    {
+        msg_perr("Unable to set fans to high speed.\n");
+        return -1;
+    }
+    return 0;
+}
+
+static int compal_pc87591_flash_enable(void) 
+{
+    int i;
+    unsigned int flashcontrolbase;
+
+    /* select logical device 0xf: shared BIOS and flash control */
+    sio_write(0x4C, 0x7, 0xF);
+    sio_write(0x4C, 0x30, 0x1); /* activate processor access */
+
+    /* get I/O base address */
+    flashcontrolbase = sio_read(0x4C, 0x61) | (sio_read(0x4C, 0x60) << 8);
+    msg_pinfo("flash control base address is 0x%x\n", flashcontrolbase);
+    for(i = 0; i < 16; i++)
+        OUTB(i * 0x10, flashcontrolbase+8); /* remove protection of flash segment i */
+
+    if(uc_send_command(0x60, 0x59) != 0) // system state notification
+    {
+        msg_perr("Unable to send System State Notification.\n");
+        return -1;
+    }
+
+    if(uc_send_data(0x60, 0xF2) != 0) // enter flash mode
+    {
+        msg_perr("Unable to put the EC into flash mode.\n");
+        return -1;
+    }
+
+    return 0;
+}
+
+static int intel_ich_gpio25_lower(void)
+{
+       return intel_ich_gpio_set(25, 0);
+}
+
+static void toshiba_flashmode_exit(void * cmdptr) 
+{
+       if(uc_send_command(0x60, 0x49) != 0) // thermal state notification
+       {
+           msg_perr("Unable to send Thermal State Notification.\n");
+           return;
+       }
+
+       if(uc_send_data(0x60, 0xA1) != 0) // set fans back to level 1
+       {
+           msg_perr("Unable to set fans back to level 1.\n");
+           return;
+       }
+}
+
+static int board_toshiba_satellite_s520(void) 
+{
+    /* Copyright (C) 2004 Toshiba and Compal. */
+    if(compal_os_takeover_fan() != 0)
+    {
+        msg_perr("compal_os_takeover_fan() is not returning 0.\n");
+        return -1;
+    }
+
+    if(compal_pc87591_flash_enable() != 0)
+    {
+        msg_perr("compal_pc87591_flash_enable() is not returning 0.\n");
+        return -1;
+    }
+
+
+    if (intel_ich_gpio25_lower() != 0)
+    { 
+        msg_perr("Unable to lower GPIO 25.\n");
+    	return -1;
+    }
+
+    register_shutdown(toshiba_flashmode_exit, NULL);
+    buses_supported = CHIP_BUSTYPE_PARALLEL;
+    return 0;
+}
+
 /*
  * Below is the list of boards which need a special "board enable" code in
  * flashrom before their ROM chip can be accessed/written to.
@@ -1963,11 +2105,11 @@ 
 	{0x10DE, 0x02F1, 0x1458, 0x5000,  0x10DE, 0x0261, 0x1458, 0x5001, NULL,          NULL,         NULL,          "GIGABYTE",    "GA-K8N51GMF",           0,   OK, nvidia_mcp_gpio3b_raise},
 	{0x10DE, 0x026C, 0x1458, 0xA102,  0x10DE, 0x0260, 0x1458, 0x5001, NULL,          NULL,         NULL,          "GIGABYTE",    "GA-K8N51GMF-9",         0,   OK, nvidia_mcp_gpio3b_raise},
 	{0x10DE, 0x0050, 0x1458, 0x0C11,  0x10DE, 0x005e, 0x1458, 0x5000, NULL,          NULL,         NULL,          "GIGABYTE",    "GA-K8N-SLI",            0,   OK, nvidia_mcp_gpio21_raise},
-	{0x8086, 0x2415, 0x103c, 0x1250,  0x10b7, 0x9200, 0x103c, 0x1247, NULL,          NULL,         NULL,          "HP",          "e-Vectra P2706T",       0,   OK, board_hp_p2706t}, 
+        {0x8086, 0x2415, 0x103c, 0x1250,  0x10b7, 0x9200, 0x103c, 0x1247, NULL,          NULL,         NULL,          "HP",          "e-Vectra P2706T",       0,   OK, board_hp_p2706t},
 	{0x1166, 0x0223, 0x103c, 0x320d,  0x14e4, 0x1678, 0x103c, 0x703e, NULL,          "hp",         "dl145_g3",    "HP",          "ProLiant DL145 G3",     0,   OK, board_hp_dl145_g3_enable},
 	{0x1166, 0x0223, 0x103c, 0x320d,  0x14e4, 0x1648, 0x103c, 0x310f, NULL,          "hp",         "dl165_g6",    "HP",          "ProLiant DL165 G6",     0,   OK, board_hp_dl165_g6_enable},
 	{0x8086, 0x2580, 0x103c, 0x2a08,  0x8086, 0x2640, 0x103c, 0x2a0a, NULL,          NULL,         NULL,          "HP",          "Puffer2-UL8E",          0,   OK, intel_ich_gpio18_raise},
-	{0x8086, 0x2415, 0x103c, 0x1249,  0x10b7, 0x9200, 0x103c, 0x1246, NULL,          NULL,         NULL,          "HP",          "Vectra VL400",          0,   OK, board_hp_vl400}, 
+        {0x8086, 0x2415, 0x103c, 0x1249,  0x10b7, 0x9200, 0x103c, 0x1246, NULL,          NULL,         NULL,          "HP",          "Vectra VL400",          0,   OK, board_hp_vl400},
 	{0x8086, 0x1a30, 0x103c, 0x1a30,  0x8086, 0x2443, 0x103c, 0x2440, "^VL420$",     NULL,         NULL,          "HP",          "Vectra VL420 SFF",      0,   OK, intel_ich_gpio22_raise},
 	{0x10de, 0x0369, 0x103c, 0x12fe,  0x10de, 0x0364, 0x103c, 0x12fe, NULL,          "hp",         "xw9400",      "HP",          "xw9400",                0,   OK, nvidia_mcp_gpio5_raise},
 	{0x8086, 0x27A0,      0,      0,  0x8086, 0x27B9,      0,      0, NULL,          "ibase",      "mb899",       "IBASE",       "MB899",                 0,   OK, intel_ich_gpio26_raise},
@@ -2000,6 +2142,7 @@ 
 	{0x1106, 0x3038, 0x0925, 0x1234,  0x1106, 0x3058, 0x15DD, 0x7609, NULL,          NULL,         NULL,          "Soyo",        "SY-7VCA",               0,   OK, via_apollo_gpo0_lower},
 	{0x1106, 0x3038, 0x0925, 0x1234,  0x1106, 0x0596, 0x1106,      0, NULL,          NULL,         NULL,          "Tekram",      "P6Pro-A5",              256, OK, NULL},
 	{0x1106, 0x3123, 0x1106, 0x3123,  0x1106, 0x3059, 0x1106, 0x4161, NULL,          NULL,         NULL,          "Termtek",     "TK-3370 (Rev:2.5B)",    0,   OK, w836xx_memw_enable_4e},
+        {0x8086, 0x24d0, 0,      0,       0x8086, 0x24d3, 0x1179, 0xff00, "^BTQ00$",     "toshiba",    "btq00",       "COMPAL",      "BTQ00",                 0,   OK, board_toshiba_satellite_s520},
 	{0x8086, 0x1076, 0x8086, 0x1176,  0x1106, 0x3059, 0x10f1, 0x2498, NULL,          NULL,         NULL,          "Tyan",        "S2498 (Tomcat K7M)",    0,   OK, w836xx_memw_enable_2e},
 	{0x1106, 0x0259, 0x1106, 0xAA07,  0x1106, 0x3227, 0x1106, 0xAA07, NULL,          NULL,         NULL,          "VIA",         "EPIA EK",               0,   NT, via_vt823x_gpio9_raise},
 	{0x1106, 0x3177, 0x1106, 0xAA01,  0x1106, 0x3123, 0x1106, 0xAA01, NULL,          NULL,         NULL,          "VIA",         "EPIA M/MII/...",        0,   OK, via_vt823x_gpio15_raise},