| Submitter | She, Kerry |
|---|---|
| Date | 2011-05-06 02:33:46 |
| Message ID | <F53A09371FB723428826B442A4B20A4105F5C765@sbjgexmb1.amd.com> |
| Download | mbox | patch |
| Permalink | /patch/2949/ |
| State | New |
| Headers | show |
Comments
On Thu, May 5, 2011 at 8:33 PM, She, Kerry <Kerry.She@amd.com> wrote: > Hello, > > >> -----Original Message----- >> From: Marc Jones [mailto:marcj303@gmail.com] >> Sent: Friday, May 06, 2011 8:52 AM >> To: Stefan Reinauer >> Cc: She, Kerry; coreboot@coreboot.org >> Subject: Re: [coreboot] [Patch 2/4] compile sb800 code without agesav5 >> >> On Fri, Apr 22, 2011 at 1:58 PM, Stefan Reinauer >> <stefan.reinauer@coreboot.org> wrote: >> > * She, Kerry <Kerry.She@amd.com> [110422 05:12]: >> >> Signed-off-by: Kerry She <Kerry.she@amd.com> >> >> >> >> SB800 CIMX code can share the AGESA V5 lib code, >> >> some platform only use sb800 cimx code, not use AGESA v5 code, >> >> compile the sb800 cimx and AGESA v5 lib code. >> >> >> >> Signed-off-by: Kerry She <Kerry.she@amd.com> >> >> >> >> Index: Makefile.inc >> >> =================================================================== >> >> --- Makefile.inc (revision 6481) >> >> +++ Makefile.inc (working copy) >> >> @@ -110,7 +110,9 @@ >> >> CFLAGS += -Werror >> >> endif >> >> ifneq ($(CONFIG_AMD_AGESA),y) >> >> -CFLAGS += -nostdinc >> >> + ifneq ($(CONFIG_AMD_CIMX_SB800),y) >> >> + CFLAGS += -nostdinc >> >> + endif >> >> endif >> >> CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame- >> pointer >> >> >> > >> > Why is that needed. Can we instead fix the code, please? >> >> Kerry, >> >> I think that this is fixed with the last patch from Frank. Can you update this patch and resend. > > I have update the patch, sb800 code not use stdinc and sse option. > Thanks > -- > kerry Acked-by: Marc Jones <marcj303@gmail.com>
Patch
Index: src/vendorcode/amd/cimx/sb800/AMDSBLIB.h =================================================================== --- src/vendorcode/amd/cimx/sb800/AMDSBLIB.h (revision 6481) +++ src/vendorcode/amd/cimx/sb800/AMDSBLIB.h (working copy) @@ -104,3 +104,14 @@ * */ void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length); + + +/* SB800 CIMx and AGESA V5 can share lib functions */ +unsigned char ReadIo8(IN unsigned short Address); +unsigned short ReadIo16(IN unsigned short Address); +unsigned int ReadIo32(IN unsigned short Address); +void WriteIo8(IN unsigned short Address, IN unsigned char Data); +void WriteIo16(IN unsigned short Address, IN unsigned short Data); +void WriteIo32(IN unsigned short Address, IN unsigned int Data); +void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value); +unsigned char ReadNumberOfCpuCores(void); Index: src/vendorcode/amd/cimx/sb800/SBCMN.c =================================================================== --- src/vendorcode/amd/cimx/sb800/SBCMN.c (revision 6481) +++ src/vendorcode/amd/cimx/sb800/SBCMN.c (working copy) @@ -329,7 +329,7 @@ { UINT32 abValue; UINT16 dwTempVar; - SB_CPUID_DATA CpuId; + CPUID_DATA CpuId; UINT8 cimNativepciesupport; UINT8 cimIrConfig; UINT8 Data; Index: src/southbridge/amd/cimx_wrapper/sb800/Amd.h =================================================================== --- src/southbridge/amd/cimx_wrapper/sb800/Amd.h (revision 6481) +++ src/southbridge/amd/cimx_wrapper/sb800/Amd.h (working copy) @@ -161,7 +161,7 @@ IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX -} SB_CPUID_DATA; +} CPUID_DATA; #define WARM_RESET 1 #define COLD_RESET 2 // Cold reset