Patchwork [07/16] Port persimmon r6584 and r6601 to e350m1: SPI prefetch early

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Submitter mbuschman@lucidmachines.com
Date 2011-06-04 06:10:35
Message ID <1307167844-13392-7-git-send-email-mbuschman@lucidmachines.com>
Download mbox | patch
Permalink /patch/3027/
State Accepted
Commit r6627
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Comments

mbuschman@lucidmachines.com - 2011-06-04 06:10:35
From: Scott Duplichan <scott@notabs.org>

Enable SPI cacheline prefetch early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
---
 src/mainboard/asrock/e350m1/romstage.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

Patch

diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 7f0b9df..41f9a6b 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -50,6 +50,13 @@  void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
   // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
   __writemsr (0xc0010062, 0);
 
+  // early enable of PrefetchEnSPIFromHost
+  if (boot_cpu())
+    {
+    __outdword (0xcf8, 0x8000a3b8);
+    __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
+    }
+
   // early enable of SPI 33 MHz fast mode read
   if (boot_cpu())
     {