From patchwork Sat Jun 4 06:10:42 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [14/16] Port persimmon r6592 to e350m1: Update GPP port configuration Date: Sat, 04 Jun 2011 06:10:42 -0000 From: mbuschman@lucidmachines.com X-Patchwork-Id: 3036 Message-Id: <1307167844-13392-14-git-send-email-mbuschman@lucidmachines.com> To: coreboot@coreboot.org Cc: Peter Stuge , Scott Duplichan From: Scott Duplichan Signed-off-by: Peter Stuge --- src/mainboard/asrock/e350m1/devicetree.cb | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index 9dceae6..d1e4a8b 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -99,12 +99,12 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 on end # PCIe PortC - device pci 15.3 on end # PCIe PortD - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx_wrapper/sb800 # end # device pci 18.0 # These seem unnecessary