Patchwork New patch to review: 7e340ba SMM: add defines for APM_CNT register

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Submitter gerrit@coreboot.org
Date 2011-06-06 16:42:05
Message ID <E1QTcsP-0005zc-Oj@ra.coresystems.de>
Download mbox | patch
Permalink /patch/3056/
State New, archived
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gerrit@coreboot.org - 2011-06-06 16:42:05
Dear list,

Sven Schnelle (svens@stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/4.

You will also find it attached for your convenience.

Regards,
gerrit

Patch

commit 7e340bae6da26a88b0913959c34ed1b99316ff73
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 5 11:33:41 2011 +0200

    SMM: add defines for APM_CNT register
    
    in the current code, the defines for the APM_CNT (0xb2) register
    are duplicated in almost every place where it is used. define those
    values in cpu/x86/smm.h, and only include this file.
    
    And while at it, fixup whitespace.
    
    Change-Id: Iae712aff53322acd51e89986c2abf4c794e25484
    Signed-off-by: Sven Schnelle <svens@stackframe.org>

diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 559b1b7..5605453 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -248,6 +248,14 @@  typedef struct {
 	};
 } smm_state_save_area_t;
 
+#define APM_CNT		0xb2
+#define APM_CNT_CST_CONTROL	0x85
+#define APM_CNT_PST_CONTROL	0x80
+#define APM_CNT_ACPI_DISABLE	0x1e
+#define APM_CNT_ACPI_ENABLE	0xe1
+#define APM_CNT_MBI_UPDATE	0xeb
+#define APM_CNT_GNVS_UPDATE	0xea
+#define APM_STS		0xb3
 
 /* SMI handler function prototypes */
 void smi_handler(u32 smm_revision);
diff --git a/src/mainboard/getac/p470/fadt.c b/src/mainboard/getac/p470/fadt.c
index dcce467..7c9b113 100644
--- a/src/mainboard/getac/p470/fadt.c
+++ b/src/mainboard/getac/p470/fadt.c
@@ -22,17 +22,12 @@ 
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
+#include <cpu/x86/smm.h>
 
 /* FIXME: This needs to go into a separate .h file
  * to be included by the ich7 smi handler, ich7 smi init
  * code and the mainboard fadt.
  */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -41,8 +36,8 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
- 	header->length = sizeof(acpi_fadt_t);
- 	header->revision = 3;
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
 	memcpy(header->oem_id, "CORE  ", 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, "CORE", 4);
@@ -52,12 +47,12 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->dsdt = (unsigned long) dsdt;
 	fadt->preferred_pm_profile = PM_MOBILE;
 
-  	fadt->sci_int = 0x9;
- 	fadt->smi_cmd = APM_CNT;
- 	fadt->acpi_enable = ACPI_ENABLE;
- 	fadt->acpi_disable = ACPI_DISABLE;
-  	fadt->s4bios_req = 0x0; // S4 command disabled
- 	fadt->pstate_cnt = PST_CONTROL;
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+	fadt->s4bios_req = 0x0; // S4 command disabled
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +70,7 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
- 	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 85;
 	fadt->flush_size = 1024;
@@ -86,78 +81,78 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->mon_alrm = 0x00;
 	fadt->century = 0x00;
 	fadt->iapc_boot_arch = 0x00;
- 	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- 			ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
- 			ACPI_FADT_DOCKING_SUPPORTED;
-
- 	fadt->reset_reg.space_id = 0;
- 	fadt->reset_reg.bit_width = 0;
- 	fadt->reset_reg.bit_offset = 0;
- 	fadt->reset_reg.resv = 0;
- 	fadt->reset_reg.addrl = 0x0;
- 	fadt->reset_reg.addrh = 0x0;
-
- 	fadt->reset_value = 0;
- 	fadt->x_firmware_ctl_l = (unsigned long)facs;
- 	fadt->x_firmware_ctl_h = 0;
- 	fadt->x_dsdt_l = (unsigned long)dsdt;
- 	fadt->x_dsdt_h = 0;
-
- 	fadt->x_pm1a_evt_blk.space_id = 1;
- 	fadt->x_pm1a_evt_blk.bit_width = 32;
- 	fadt->x_pm1a_evt_blk.bit_offset = 0;
- 	fadt->x_pm1a_evt_blk.resv = 0;
- 	fadt->x_pm1a_evt_blk.addrl = pmbase;
- 	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_evt_blk.space_id = 1;
- 	fadt->x_pm1b_evt_blk.bit_width = 0;
- 	fadt->x_pm1b_evt_blk.bit_offset = 0;
- 	fadt->x_pm1b_evt_blk.resv = 0;
- 	fadt->x_pm1b_evt_blk.addrl = 0x0;
- 	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1a_cnt_blk.space_id = 1;
- 	fadt->x_pm1a_cnt_blk.bit_width = 16;
- 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1a_cnt_blk.resv = 0;
- 	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_cnt_blk.space_id = 1;
- 	fadt->x_pm1b_cnt_blk.bit_width = 0;
- 	fadt->x_pm1b_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1b_cnt_blk.resv = 0;
- 	fadt->x_pm1b_cnt_blk.addrl = 0x0;
- 	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm2_cnt_blk.space_id = 1;
- 	fadt->x_pm2_cnt_blk.bit_width = 8;
- 	fadt->x_pm2_cnt_blk.bit_offset = 0;
- 	fadt->x_pm2_cnt_blk.resv = 0;
- 	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
- 	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm_tmr_blk.space_id = 1;
- 	fadt->x_pm_tmr_blk.bit_width = 32;
- 	fadt->x_pm_tmr_blk.bit_offset = 0;
- 	fadt->x_pm_tmr_blk.resv = 0;
- 	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- 	fadt->x_pm_tmr_blk.addrh = 0x0;
-
- 	fadt->x_gpe0_blk.space_id = 1;
- 	fadt->x_gpe0_blk.bit_width = 64;
- 	fadt->x_gpe0_blk.bit_offset = 0;
- 	fadt->x_gpe0_blk.resv = 0;
- 	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
- 	fadt->x_gpe0_blk.addrh = 0x0;
-
- 	fadt->x_gpe1_blk.space_id = 1;
- 	fadt->x_gpe1_blk.bit_width = 0;
- 	fadt->x_gpe1_blk.bit_offset = 0;
- 	fadt->x_gpe1_blk.resv = 0;
- 	fadt->x_gpe1_blk.addrl = 0x0;
- 	fadt->x_gpe1_blk.addrh = 0x0;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
+			ACPI_FADT_DOCKING_SUPPORTED;
+
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
 
 	header->checksum =
 	    acpi_checksum((void *) fadt, header->length);
diff --git a/src/mainboard/ibase/mb899/fadt.c b/src/mainboard/ibase/mb899/fadt.c
index a0e381f..44d4c9b 100644
--- a/src/mainboard/ibase/mb899/fadt.c
+++ b/src/mainboard/ibase/mb899/fadt.c
@@ -20,17 +20,7 @@ 
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
-
-/* FIXME: This needs to go into a separate .h file
- * to be included by the ich7 smi handler, ich7 smi init
- * code and the mainboard fadt.
- */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
+#include <cpu/x86/smm.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -39,8 +29,8 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
- 	header->length = sizeof(acpi_fadt_t);
- 	header->revision = 3;
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
 	memcpy(header->oem_id, "CORE  ", 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, "CORE", 4);
@@ -51,12 +41,12 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->model = 1;
 	fadt->preferred_pm_profile = PM_MOBILE;
 
-  	fadt->sci_int = 0x9;
- 	fadt->smi_cmd = APM_CNT;
- 	fadt->acpi_enable = ACPI_ENABLE;
- 	fadt->acpi_disable = ACPI_DISABLE;
-  	fadt->s4bios_req = 0x0;
- 	fadt->pstate_cnt = PST_CONTROL;
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +65,7 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
- 	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 85;
 	fadt->flush_size = 1024;
@@ -87,78 +77,78 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->century = 0x00;
 	fadt->iapc_boot_arch = 0x03;
 
- 	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
 			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
 			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
 
- 	fadt->reset_reg.space_id = 0;
- 	fadt->reset_reg.bit_width = 0;
- 	fadt->reset_reg.bit_offset = 0;
- 	fadt->reset_reg.resv = 0;
- 	fadt->reset_reg.addrl = 0x0;
- 	fadt->reset_reg.addrh = 0x0;
-
- 	fadt->reset_value = 0;
- 	fadt->x_firmware_ctl_l = (unsigned long)facs;
- 	fadt->x_firmware_ctl_h = 0;
- 	fadt->x_dsdt_l = (unsigned long)dsdt;
- 	fadt->x_dsdt_h = 0;
-
- 	fadt->x_pm1a_evt_blk.space_id = 1;
- 	fadt->x_pm1a_evt_blk.bit_width = 32;
- 	fadt->x_pm1a_evt_blk.bit_offset = 0;
- 	fadt->x_pm1a_evt_blk.resv = 0;
- 	fadt->x_pm1a_evt_blk.addrl = pmbase;
- 	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_evt_blk.space_id = 1;
- 	fadt->x_pm1b_evt_blk.bit_width = 0;
- 	fadt->x_pm1b_evt_blk.bit_offset = 0;
- 	fadt->x_pm1b_evt_blk.resv = 0;
- 	fadt->x_pm1b_evt_blk.addrl = 0x0;
- 	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1a_cnt_blk.space_id = 1;
- 	fadt->x_pm1a_cnt_blk.bit_width = 16;
- 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1a_cnt_blk.resv = 0;
- 	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_cnt_blk.space_id = 1;
- 	fadt->x_pm1b_cnt_blk.bit_width = 0;
- 	fadt->x_pm1b_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1b_cnt_blk.resv = 0;
- 	fadt->x_pm1b_cnt_blk.addrl = 0x0;
- 	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm2_cnt_blk.space_id = 1;
- 	fadt->x_pm2_cnt_blk.bit_width = 8;
- 	fadt->x_pm2_cnt_blk.bit_offset = 0;
- 	fadt->x_pm2_cnt_blk.resv = 0;
- 	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
- 	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm_tmr_blk.space_id = 1;
- 	fadt->x_pm_tmr_blk.bit_width = 32;
- 	fadt->x_pm_tmr_blk.bit_offset = 0;
- 	fadt->x_pm_tmr_blk.resv = 0;
- 	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- 	fadt->x_pm_tmr_blk.addrh = 0x0;
-
- 	fadt->x_gpe0_blk.space_id = 1;
- 	fadt->x_gpe0_blk.bit_width = 64;
- 	fadt->x_gpe0_blk.bit_offset = 0;
- 	fadt->x_gpe0_blk.resv = 0;
- 	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
- 	fadt->x_gpe0_blk.addrh = 0x0;
-
- 	fadt->x_gpe1_blk.space_id = 1;
- 	fadt->x_gpe1_blk.bit_width = 0;
- 	fadt->x_gpe1_blk.bit_offset = 0;
- 	fadt->x_gpe1_blk.resv = 0;
- 	fadt->x_gpe1_blk.addrl = 0x0;
- 	fadt->x_gpe1_blk.addrh = 0x0;
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
 
 	header->checksum =
 	    acpi_checksum((void *) fadt, header->length);
diff --git a/src/mainboard/intel/d945gclf/fadt.c b/src/mainboard/intel/d945gclf/fadt.c
index 5b2df8b..1a66eef 100644
--- a/src/mainboard/intel/d945gclf/fadt.c
+++ b/src/mainboard/intel/d945gclf/fadt.c
@@ -20,17 +20,7 @@ 
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
-
-/* FIXME: This needs to go into a separate .h file
- * to be included by the ich7 smi handler, ich7 smi init
- * code and the mainboard fadt.
- */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
+#include <cpu/x86/smm.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -39,8 +29,8 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
- 	header->length = sizeof(acpi_fadt_t);
- 	header->revision = 3;
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
 	memcpy(header->oem_id, "CORE  ", 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, "CORE", 4);
@@ -51,12 +41,12 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->model = 1;
 	fadt->preferred_pm_profile = PM_MOBILE;
 
-  	fadt->sci_int = 0x9;
- 	fadt->smi_cmd = APM_CNT;
- 	fadt->acpi_enable = ACPI_ENABLE;
- 	fadt->acpi_disable = ACPI_DISABLE;
-  	fadt->s4bios_req = 0x0;
- 	fadt->pstate_cnt = PST_CONTROL;
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +65,7 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
- 	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 85;
 	fadt->flush_size = 1024;
@@ -87,78 +77,78 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->century = 0x00;
 	fadt->iapc_boot_arch = 0x03;
 
- 	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
-			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+		ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
 			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
 
- 	fadt->reset_reg.space_id = 0;
- 	fadt->reset_reg.bit_width = 0;
- 	fadt->reset_reg.bit_offset = 0;
- 	fadt->reset_reg.resv = 0;
- 	fadt->reset_reg.addrl = 0x0;
- 	fadt->reset_reg.addrh = 0x0;
-
- 	fadt->reset_value = 0;
- 	fadt->x_firmware_ctl_l = (unsigned long)facs;
- 	fadt->x_firmware_ctl_h = 0;
- 	fadt->x_dsdt_l = (unsigned long)dsdt;
- 	fadt->x_dsdt_h = 0;
-
- 	fadt->x_pm1a_evt_blk.space_id = 1;
- 	fadt->x_pm1a_evt_blk.bit_width = 32;
- 	fadt->x_pm1a_evt_blk.bit_offset = 0;
- 	fadt->x_pm1a_evt_blk.resv = 0;
- 	fadt->x_pm1a_evt_blk.addrl = pmbase;
- 	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_evt_blk.space_id = 1;
- 	fadt->x_pm1b_evt_blk.bit_width = 0;
- 	fadt->x_pm1b_evt_blk.bit_offset = 0;
- 	fadt->x_pm1b_evt_blk.resv = 0;
- 	fadt->x_pm1b_evt_blk.addrl = 0x0;
- 	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1a_cnt_blk.space_id = 1;
- 	fadt->x_pm1a_cnt_blk.bit_width = 16;
- 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1a_cnt_blk.resv = 0;
- 	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_cnt_blk.space_id = 1;
- 	fadt->x_pm1b_cnt_blk.bit_width = 0;
- 	fadt->x_pm1b_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1b_cnt_blk.resv = 0;
- 	fadt->x_pm1b_cnt_blk.addrl = 0x0;
- 	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm2_cnt_blk.space_id = 1;
- 	fadt->x_pm2_cnt_blk.bit_width = 8;
- 	fadt->x_pm2_cnt_blk.bit_offset = 0;
- 	fadt->x_pm2_cnt_blk.resv = 0;
- 	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
- 	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm_tmr_blk.space_id = 1;
- 	fadt->x_pm_tmr_blk.bit_width = 32;
- 	fadt->x_pm_tmr_blk.bit_offset = 0;
- 	fadt->x_pm_tmr_blk.resv = 0;
- 	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- 	fadt->x_pm_tmr_blk.addrh = 0x0;
-
- 	fadt->x_gpe0_blk.space_id = 1;
- 	fadt->x_gpe0_blk.bit_width = 64;
- 	fadt->x_gpe0_blk.bit_offset = 0;
- 	fadt->x_gpe0_blk.resv = 0;
- 	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
- 	fadt->x_gpe0_blk.addrh = 0x0;
-
- 	fadt->x_gpe1_blk.space_id = 1;
- 	fadt->x_gpe1_blk.bit_width = 0;
- 	fadt->x_gpe1_blk.bit_offset = 0;
- 	fadt->x_gpe1_blk.resv = 0;
- 	fadt->x_gpe1_blk.addrl = 0x0;
- 	fadt->x_gpe1_blk.addrh = 0x0;
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
 
 	header->checksum =
 	    acpi_checksum((void *) fadt, header->length);
diff --git a/src/mainboard/intel/eagleheights/fadt.c b/src/mainboard/intel/eagleheights/fadt.c
index 86f4ba1..992c318 100644
--- a/src/mainboard/intel/eagleheights/fadt.c
+++ b/src/mainboard/intel/eagleheights/fadt.c
@@ -23,6 +23,7 @@ 
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
+#include <cpu/x86/smm.h>
 
 #define ACPI_PM1_STS        (pmbase + 0x00)
 #define ACPI_PM1_EN         (pmbase + 0x02)
@@ -67,12 +68,12 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->preferred_pm_profile = 7; /* Performance Server */
 	fadt->sci_int = 0x9;
 #if CONFIG_HAVE_SMI_HANDLER == 1
-	fadt->smi_cmd = 0xb2;
+	fadt->smi_cmd = APM_CNT;
 #else
 	fadt->smi_cmd = 0x00;
 #endif
-	fadt->acpi_enable = 0xe1;
-	fadt->acpi_disable = 0x1e;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
 	fadt->s4bios_req = 0x0;
 	fadt->pstate_cnt = 0xe2;
 
diff --git a/src/mainboard/iwave/iWRainbowG6/fadt.c b/src/mainboard/iwave/iWRainbowG6/fadt.c
index ae58bbf..bc4a0d4 100644
--- a/src/mainboard/iwave/iWRainbowG6/fadt.c
+++ b/src/mainboard/iwave/iWRainbowG6/fadt.c
@@ -20,17 +20,7 @@ 
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
-
-/* FIXME: This needs to go into a separate .h file
- * to be included by the ich7 smi handler, ich7 smi init
- * code and the mainboard fadt.
- */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
+#include <cpu/x86/smm.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -54,10 +44,10 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	fadt->sci_int = 0x9;
 	fadt->smi_cmd = APM_CNT;
-	fadt->acpi_enable = ACPI_ENABLE;
-	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
 	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = PST_CONTROL;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -76,7 +66,7 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
-	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 85;
 	fadt->flush_size = 1024;
diff --git a/src/mainboard/kontron/986lcd-m/fadt.c b/src/mainboard/kontron/986lcd-m/fadt.c
index 12aeac0..f945d3f 100644
--- a/src/mainboard/kontron/986lcd-m/fadt.c
+++ b/src/mainboard/kontron/986lcd-m/fadt.c
@@ -20,17 +20,7 @@ 
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
-
-/* FIXME: This needs to go into a separate .h file
- * to be included by the ich7 smi handler, ich7 smi init
- * code and the mainboard fadt.
- */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
+#include <cpu/x86/smm.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -39,8 +29,8 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
- 	header->length = sizeof(acpi_fadt_t);
- 	header->revision = 3;
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
 	memcpy(header->oem_id, "CORE  ", 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, "CORE", 4);
@@ -51,12 +41,12 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->model = 1;
 	fadt->preferred_pm_profile = PM_MOBILE;
 
-  	fadt->sci_int = 0x9;
- 	fadt->smi_cmd = APM_CNT;
- 	fadt->acpi_enable = ACPI_ENABLE;
- 	fadt->acpi_disable = ACPI_DISABLE;
-  	fadt->s4bios_req = 0x0;
- 	fadt->pstate_cnt = PST_CONTROL;
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +65,7 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
- 	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 85;
 	fadt->flush_size = 1024;
@@ -87,79 +77,79 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->century = 0x00;
 	fadt->iapc_boot_arch = 0x03;
 
- 	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
 			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
 			ACPI_FADT_RESET_REGISTER |
 			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
 
- 	fadt->reset_reg.space_id = 1;
- 	fadt->reset_reg.bit_width = 8;
- 	fadt->reset_reg.bit_offset = 0;
- 	fadt->reset_reg.resv = 0;
- 	fadt->reset_reg.addrl = 0xcf9;
- 	fadt->reset_reg.addrh = 0;
-
- 	fadt->reset_value = 6;
- 	fadt->x_firmware_ctl_l = (unsigned long)facs;
- 	fadt->x_firmware_ctl_h = 0;
- 	fadt->x_dsdt_l = (unsigned long)dsdt;
- 	fadt->x_dsdt_h = 0;
-
- 	fadt->x_pm1a_evt_blk.space_id = 1;
- 	fadt->x_pm1a_evt_blk.bit_width = 32;
- 	fadt->x_pm1a_evt_blk.bit_offset = 0;
- 	fadt->x_pm1a_evt_blk.resv = 0;
- 	fadt->x_pm1a_evt_blk.addrl = pmbase;
- 	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_evt_blk.space_id = 1;
- 	fadt->x_pm1b_evt_blk.bit_width = 0;
- 	fadt->x_pm1b_evt_blk.bit_offset = 0;
- 	fadt->x_pm1b_evt_blk.resv = 0;
- 	fadt->x_pm1b_evt_blk.addrl = 0x0;
- 	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1a_cnt_blk.space_id = 1;
- 	fadt->x_pm1a_cnt_blk.bit_width = 16;
- 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1a_cnt_blk.resv = 0;
- 	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_cnt_blk.space_id = 1;
- 	fadt->x_pm1b_cnt_blk.bit_width = 0;
- 	fadt->x_pm1b_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1b_cnt_blk.resv = 0;
- 	fadt->x_pm1b_cnt_blk.addrl = 0x0;
- 	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm2_cnt_blk.space_id = 1;
- 	fadt->x_pm2_cnt_blk.bit_width = 8;
- 	fadt->x_pm2_cnt_blk.bit_offset = 0;
- 	fadt->x_pm2_cnt_blk.resv = 0;
- 	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
- 	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm_tmr_blk.space_id = 1;
- 	fadt->x_pm_tmr_blk.bit_width = 32;
- 	fadt->x_pm_tmr_blk.bit_offset = 0;
- 	fadt->x_pm_tmr_blk.resv = 0;
- 	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- 	fadt->x_pm_tmr_blk.addrh = 0x0;
-
- 	fadt->x_gpe0_blk.space_id = 1;
- 	fadt->x_gpe0_blk.bit_width = 64;
- 	fadt->x_gpe0_blk.bit_offset = 0;
- 	fadt->x_gpe0_blk.resv = 0;
- 	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
- 	fadt->x_gpe0_blk.addrh = 0x0;
-
- 	fadt->x_gpe1_blk.space_id = 1;
- 	fadt->x_gpe1_blk.bit_width = 0;
- 	fadt->x_gpe1_blk.bit_offset = 0;
- 	fadt->x_gpe1_blk.resv = 0;
- 	fadt->x_gpe1_blk.addrl = 0x0;
- 	fadt->x_gpe1_blk.addrh = 0x0;
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
 
 	header->checksum =
 	    acpi_checksum((void *) fadt, header->length);
diff --git a/src/mainboard/lenovo/t60/fadt.c b/src/mainboard/lenovo/t60/fadt.c
index e45db8a..9f73f9c 100644
--- a/src/mainboard/lenovo/t60/fadt.c
+++ b/src/mainboard/lenovo/t60/fadt.c
@@ -22,17 +22,12 @@ 
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
+#include <cpu/x86/smm.h>
 
 /* FIXME: This needs to go into a separate .h file
  * to be included by the ich7 smi handler, ich7 smi init
  * code and the mainboard fadt.
  */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -54,10 +49,10 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->preferred_pm_profile = PM_MOBILE;
 	fadt->sci_int = 0x9;
 	fadt->smi_cmd = APM_CNT;
-	fadt->acpi_enable = ACPI_ENABLE;
-	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
 	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = PST_CONTROL;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +70,7 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
-	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 0x23;
 	fadt->flush_size = 0;
diff --git a/src/mainboard/lenovo/x60/fadt.c b/src/mainboard/lenovo/x60/fadt.c
index e45db8a..9f73f9c 100644
--- a/src/mainboard/lenovo/x60/fadt.c
+++ b/src/mainboard/lenovo/x60/fadt.c
@@ -22,17 +22,12 @@ 
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
+#include <cpu/x86/smm.h>
 
 /* FIXME: This needs to go into a separate .h file
  * to be included by the ich7 smi handler, ich7 smi init
  * code and the mainboard fadt.
  */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -54,10 +49,10 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->preferred_pm_profile = PM_MOBILE;
 	fadt->sci_int = 0x9;
 	fadt->smi_cmd = APM_CNT;
-	fadt->acpi_enable = ACPI_ENABLE;
-	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
 	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = PST_CONTROL;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +70,7 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
-	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 0x23;
 	fadt->flush_size = 0;
diff --git a/src/mainboard/lenovo/x60/mainboard_smi.c b/src/mainboard/lenovo/x60/mainboard_smi.c
index 5e0f6a9..78f7f2a 100644
--- a/src/mainboard/lenovo/x60/mainboard_smi.c
+++ b/src/mainboard/lenovo/x60/mainboard_smi.c
@@ -75,4 +75,3 @@  int mainboard_io_trap_handler(int smif)
 	 * On failure, the IO Trap Handler returns a value != 0 */
 	return 0;
 }
-
diff --git a/src/mainboard/roda/rk886ex/fadt.c b/src/mainboard/roda/rk886ex/fadt.c
index e45db8a..b07856a 100644
--- a/src/mainboard/roda/rk886ex/fadt.c
+++ b/src/mainboard/roda/rk886ex/fadt.c
@@ -22,17 +22,7 @@ 
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
-
-/* FIXME: This needs to go into a separate .h file
- * to be included by the ich7 smi handler, ich7 smi init
- * code and the mainboard fadt.
- */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
+#include <cpu/x86/smm.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -54,10 +44,10 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->preferred_pm_profile = PM_MOBILE;
 	fadt->sci_int = 0x9;
 	fadt->smi_cmd = APM_CNT;
-	fadt->acpi_enable = ACPI_ENABLE;
-	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
 	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = PST_CONTROL;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +65,7 @@  void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
-	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 0x23;
 	fadt->flush_size = 0;
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 4875ba7..1d306da 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -30,15 +30,6 @@ 
 
 #define DEBUG_SMI
 
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
-#define   MBI_UPDATE    0xeb
-#define APM_STS		0xb3
-
 /* I830M */
 #define SMRAM		0x90
 #define   D_OPEN	(1 << 6)
@@ -370,33 +361,33 @@  static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
 
 	reg8 = inb(APM_CNT);
 	switch (reg8) {
-	case CST_CONTROL:
+	case APM_CNT_CST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
 		printk(BIOS_DEBUG, "C-state control\n");
 		break;
-	case PST_CONTROL:
+	case APM_CNT_PST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
 		printk(BIOS_DEBUG, "P-state control\n");
 		break;
-	case ACPI_DISABLE:
+	case APM_CNT_ACPI_DISABLE:
 		pmctrl = inl(pmbase + PM1_CNT);
 		pmctrl &= ~SCI_EN;
 		outl(pmctrl, pmbase + PM1_CNT);
 		printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
 		break;
-	case ACPI_ENABLE:
+	case APM_CNT_ACPI_ENABLE:
 		pmctrl = inl(pmbase + PM1_CNT);
 		pmctrl |= SCI_EN;
 		outl(pmctrl, pmbase + PM1_CNT);
 		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
-	case GNVS_UPDATE:
+	case APM_CNT_GNVS_UPDATE:
 		if (smm_initialized) {
 			printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
 			return;
@@ -407,7 +398,7 @@  static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
 		smm_initialized = 1;
 		printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
 		break;
-	case MBI_UPDATE: // FIXME
+	case APM_CNT_MBI_UPDATE: // FIXME
 		if (mbi_initialized) {
 			printk(BIOS_DEBUG, "SMI#: mbi already registered!\n");
 			return;
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 7feb76a..394f161 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -29,6 +29,7 @@ 
 #include <arch/ioapic.h>
 #include <cpu/cpu.h>
 #include "i82801gx.h"
+#include <cpu/x86/smm.h>
 
 #define NMI_OFF	0
 
@@ -341,13 +342,13 @@  static void i82801gx_lock_smm(struct device *dev)
 #endif
 
 #if ENABLE_ACPI_MODE_IN_COREBOOT
-	printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
-	outb(0xe1, 0xb2); // Enable ACPI mode
-	printk(BIOS_DEBUG, "done.\n");
+		printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
+		outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
+		printk(BIOS_DEBUG, "done.\n");
 #else
-	printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
-	outb(0x1e, 0xb2); // Disable ACPI mode
-	printk(BIOS_DEBUG, "done.\n");
+		printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
+		outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
+		printk(BIOS_DEBUG, "done.\n");
 #endif
 	/* Don't allow evil boot loaders, kernels, or
 	 * userspace applications to deceive us:
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index bccf6d5..9befbf9 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -28,14 +28,6 @@ 
 #include <device/pci_def.h>
 #include "i82801gx.h"
 
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
-#define APM_STS		0xb3
-
 /* I945 */
 #define SMRAM		0x9d
 #define   D_OPEN	(1 << 6)
@@ -366,33 +358,33 @@  static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
 		return;
 
 	switch (reg8) {
-	case CST_CONTROL:
+	case APM_CNT_CST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
 		printk(BIOS_DEBUG, "C-state control\n");
 		break;
-	case PST_CONTROL:
+	case APM_CNT_PST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
 		printk(BIOS_DEBUG, "P-state control\n");
 		break;
-	case ACPI_DISABLE:
+	case APM_CNT_ACPI_DISABLE:
 		pmctrl = inl(pmbase + PM1_CNT);
 		pmctrl &= ~SCI_EN;
 		outl(pmctrl, pmbase + PM1_CNT);
 		printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
 		break;
-	case ACPI_ENABLE:
+	case APM_CNT_ACPI_ENABLE:
 		pmctrl = inl(pmbase + PM1_CNT);
 		pmctrl |= SCI_EN;
 		outl(pmctrl, pmbase + PM1_CNT);
 		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
-	case GNVS_UPDATE:
+	case APM_CNT_GNVS_UPDATE:
 		if (smm_initialized) {
 			printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
 			return;
diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c
index 127f627..99ae018 100644
--- a/src/southbridge/intel/sch/smihandler.c
+++ b/src/southbridge/intel/sch/smihandler.c
@@ -28,11 +28,6 @@ 
 
 #define DEBUG_SMI
 
-#define APM_CNT		0xb2
-#define APM_STS		0xb3
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-
 /* I945 */
 #define SMRAM		0x9d
 #define   D_OPEN	(1 << 6)
diff --git a/src/southbridge/via/vt8237r/smihandler.c b/src/southbridge/via/vt8237r/smihandler.c
index 0c8ff2f..357e517 100644
--- a/src/southbridge/via/vt8237r/smihandler.c
+++ b/src/southbridge/via/vt8237r/smihandler.c
@@ -29,14 +29,6 @@ 
 #include <device/pci_def.h>
 #include "vt8237r.h"
 
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
-#define APM_STS		0xb3
-
 #include "nvs.h"
 
 /* While we read PMBASE dynamically in case it changed, let's
@@ -158,33 +150,33 @@  static void southbridge_smi_cmd(unsigned int node, smm_state_save_area_t *state_
 
 	reg8 = inb(pmbase + 0x2f);
 	switch (reg8) {
-	case CST_CONTROL:
+	case APM_CNT_CST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
 		printk(BIOS_DEBUG, "C-state control\n");
 		break;
-	case PST_CONTROL:
+	case APM_CNT_PST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
 		printk(BIOS_DEBUG, "P-state control\n");
 		break;
-	case ACPI_DISABLE:
+	case APM_CNT_ACPI_DISABLE:
 		pmctrl = inw(pmbase + PM1_CNT);
 		pmctrl &= ~SCI_EN;
 		outw(pmctrl, pmbase + PM1_CNT);
 		printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
 		break;
-	case ACPI_ENABLE:
+	case APM_CNT_ACPI_ENABLE:
 		pmctrl = inw(pmbase + PM1_CNT);
 		pmctrl |= SCI_EN;
 		outw(pmctrl, pmbase + PM1_CNT);
 		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
-	case GNVS_UPDATE:
+	case APM_CNT_GNVS_UPDATE:
 		if (smm_initialized) {
 			printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
 			return;