Patchwork New patch to review: 0d807b9 X60: handle EC events in SMM if ACPI is disabled

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Submitter gerrit@coreboot.org
Date 2011-06-12 14:50:04
Message ID <E1QVlzI-0008Vk-RW@ra.coresystems.de>
Download mbox | patch
Permalink /patch/3117/
State New, archived
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Comments

gerrit@coreboot.org - 2011-06-12 14:50:04
Sven Schnelle (svens@stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/27

-gerrit

Patch

commit 0d807b9ec65d1525be6c8f2b75cc5287ed71be33
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 12 16:49:13 2011 +0200

    X60: handle EC events in SMM if ACPI is disabled
    
    Change-Id: I0fee890bd2d667b54965201f5c90da3656d7af5c
    Signed-off-by: Sven Schnelle <svens@stackframe.org>

diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index b708dce..42a45d1 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -53,13 +53,13 @@  chip northbridge/intel/i945
 			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
 			#  2 SCI (if corresponding GPIO_EN bit is also set)
 			register "gpi13_routing" = "2"
-			register "gpi12_routing" = "2"
+			register "gpi12_routing" = "1"
 			register "gpi8_routing" = "2"
 
 			register "sata_ahci" = "0x0"
 
 			register "gpe0_en" = "0x11000006"
-
+			register "alt_gp_smi_en" = "0x1000"
 			device pci 1b.0 on # Audio Cnotroller
 				subsystemid 0x17aa 0x2010
 			end
diff --git a/src/mainboard/lenovo/x60/mainboard_smi.c b/src/mainboard/lenovo/x60/mainboard_smi.c
index 202fe3d..a25c720 100644
--- a/src/mainboard/lenovo/x60/mainboard_smi.c
+++ b/src/mainboard/lenovo/x60/mainboard_smi.c
@@ -24,6 +24,7 @@ 
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include "southbridge/intel/i82801gx/nvs.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
 #include <ec/acpi/ec.h>
 #include <pc80/mc146818rtc.h>
 #include <ec/lenovo/h8/h8.h>
@@ -98,3 +99,94 @@  int mainboard_io_trap_handler(int smif)
 	 * On failure, the IO Trap Handler returns a value != 0 */
 	return 0;
 }
+
+static void mainboard_smi_brightness_up(void)
+{
+	u8 value;
+
+	if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
+		pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
+}
+
+static void mainboard_smi_brightness_down(void)
+{
+	u8 value;
+
+	if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
+		pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value - 0x10) & 0xf0);
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+	u8 status = inb(EC_SC);
+	u8 event;
+
+	if (!(status & EC_SCI_EVT))
+		return;
+
+	event = ec_query();
+	printk(BIOS_DEBUG, "EC event %02x\n", event);
+
+	switch(event) {
+		/* brightness up */
+		case 0x14:
+			mainboard_smi_brightness_up();
+			mainboard_smi_save_cmos();
+			break;
+		/* brightness down */
+		case 0x15:
+			mainboard_smi_brightness_down();
+			mainboard_smi_save_cmos();
+			break;
+		default:
+			break;
+	}
+}
+
+void mainboard_smi_gpi(u16 gpi)
+{
+	if (gpi & (1 << 12))
+		mainboard_smi_handle_ec_sci();
+}
+
+int mainboard_apm_cnt(u8 data)
+{
+	u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+	u8 tmp;
+
+	printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data);
+
+	if (!pmbase)
+		return 0;
+
+	switch(data) {
+		case APM_CNT_ACPI_ENABLE:
+			/* use 0x1600/0x1604 to prevent races with userspace */
+			ec_set_ports(0x1604, 0x1600);
+			/* route H8SCI to SCI */
+			outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+			tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+			tmp &= ~0x03;
+			tmp |= 0x02;
+			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+			/* discard all events, and enable attention */
+			ec_write(0x80, 0x01);
+			break;
+		case APM_CNT_ACPI_DISABLE:
+			/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+			   provide a EC query function */
+			ec_set_ports(0x66, 0x62);
+			/* route H8SCI# to SMI */
+			outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
+			tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+			tmp &= ~0x03;
+			tmp |= 0x01;
+			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+			/* discard all events, and enable attention */
+			ec_write(0x80, 0x01);
+			break;
+		default:
+			break;
+	}
+	return 0;
+}