Patchwork New patch to review: 35e1cb4 Move SB800 clock init earlier

login
register
about
Submitter gerrit@coreboot.org
Date 2011-06-15 04:20:33
Message ID <E1QWhaj-0006S1-JT@ra.coresystems.de>
Download mbox | patch
Permalink /patch/3140/
State New, archived
Headers show

Comments

gerrit@coreboot.org - 2011-06-15 04:20:33
Marshall Buschman (mbuschman@lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/31

-gerrit

Patch

commit 35e1cb4068e883780c26d4819371d291d630d4b3
Author: Scott Duplichan <scott@notabs.org>
Date:   Tue Jun 14 23:03:20 2011 -0500

    Move SB800 clock init earlier
    
    Committing Scott's e350m1 changes (svn r6585):
    Move SB800 clock init earlier,
    Fixes problem where initial serial port output is garbled.
    
    Change-Id: I649aa92ef6cc53a684ae79c1fe99b9fd17db140e
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>

diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 7d25ec1..4f74566 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -54,6 +54,20 @@  void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
 	__writemsr(0xc0010062, 0);
+	
+	if (boot_cpu())	{
+		u8 reg8;
+		// SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register
+		outb(0x24, 0xCD6);
+		reg8 = inb(0xCD7);
+		reg8 |= 1;
+		reg8 &= ~(1 << 1);
+		outb(reg8, 0xCD7);
+
+		// program SB800 MiscCntrl
+		*(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
+		*(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
+	}
 
 	// early enable of PrefetchEnSPIFromHost
 	if (boot_cpu()) {
@@ -80,17 +94,6 @@  void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 		console_init();
 	}
-	//reg8 = pmio_read(0x24);
-	outb(0x24, 0xCD6);
-	reg8 = inb(0xCD7);
-	reg8 |= 1;
-	reg8 &= ~(1 << 1);
-	//pmio_write(0x24, reg8);
-	outb(0x24, 0xCD6);
-	outb(reg8, 0xCD7);
-
-	*(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2));	/* 48Mhz */
-	*(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1;	/* 48Mhz */
 
 	/* Halt if there was a built in self test failure */
 	post_code(0x34);