Patchwork build failure: cannot move location counter backwards

I'm new to coreboot and just trying to get it to boot into qemu. I've
tried using SeaBios as well as just copying "yes" to payload.elf. I
updated the Makefile to use gcc 4.5 instead of the 4.4 that ships with
my distribution (Ubuntu 10.10):

dvhart@doubt:~/source/coreboot.svn
$ gcc --version
gcc (Ubuntu/Linaro 4.4.4-14ubuntu5) 4.4.5
Copyright (C) 2010 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

dvhart@doubt:~/source/coreboot.svn
$ gcc-4.5 --version
gcc-4.5 (Ubuntu/Linaro 4.5.1-7ubuntu2) 4.5.1
Copyright (C) 2010 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.


I followed the instructions here:
http://www.coreboot.org/Build_HOWTO
to configure for qemux86 with a 256K ROM.

The build output and resulting failure follow. Am I doing something dumb
or have I hit a legitimate bug?

$ make
    GEN        bootblock/ldscript.ld
    LINK       bootblock.elf
    OBJCOPY    coreboot.bootblock
    CC         lib/memset.romstage.o
    CC         lib/memcpy.romstage.o
    CC         lib/memcmp.romstage.o
    CC         lib/cbfs.romstage.o
    CC         lib/lzma.romstage.o
    CC         lib/uart8250.romstage.o
    CC         console/vtxprintf.romstage.o
    CC         console/post.romstage.o
    CC         console/die.romstage.o
    GEN        build.h
    ROMCC      romstage.inc
    GEN        romstage/crt0.S
    CC         mainboard/emulation/qemu-x86/crt0.s
    CC         mainboard/emulation/qemu-x86/crt0.romstage.o
    CC         arch/x86/lib/romstage_console.romstage.o
    CC         arch/x86/lib/cbfs_and_run.romstage.o
    CC         southbridge/intel/i82371eb/early_pm.romstage.o
    CC         southbridge/intel/i82371eb/early_smbus.romstage.o
    GEN        romstage/ldscript.ld
    LINK       coreboot.romstage
    CBFS       coreboot.pre
    CC         arch/x86/lib/c_start.ramstage.o
    CC         console/uart8250_console.driver.o
    CC         southbridge/intel/i82371eb/i82371eb.driver.o
    CC         southbridge/intel/i82371eb/isa.driver.o
    CC         southbridge/intel/i82371eb/ide.driver.o
    CC         southbridge/intel/i82371eb/usb.driver.o
    CC         southbridge/intel/i82371eb/smbus.driver.o
    CC         southbridge/intel/i82371eb/reset.driver.o
    CC         mainboard/emulation/qemu-x86/static.ramstage.o
    CC         lib/memset.ramstage.o
    CC         lib/memcpy.ramstage.o
    CC         lib/memcmp.ramstage.o
    CC         lib/memmove.ramstage.o
    CC         lib/malloc.ramstage.o
    CC         lib/delay.ramstage.o
    CC         lib/fallback_boot.ramstage.o
    CC         lib/compute_ip_checksum.ramstage.o
    CC         lib/version.ramstage.o
    CC         lib/cbfs.ramstage.o
    CC         lib/lzma.ramstage.o
    CC         lib/gcc.ramstage.o
    CC         lib/clog2.ramstage.o
    CC         lib/cbmem.ramstage.o
    CC         lib/uart8250.ramstage.o
    CC         boot/hardwaremain.ramstage.o
    CC         boot/selfboot.ramstage.o
    CC         console/printk.ramstage.o
    CC         console/console.ramstage.o
    CC         console/vtxprintf.ramstage.o
    CC         console/vsprintf.ramstage.o
    CC         console/post.ramstage.o
    CC         console/die.ramstage.o
    CC         devices/device.ramstage.o
    CC         devices/root_device.ramstage.o
    CC         devices/device_util.ramstage.o
    CC         devices/pci_device.ramstage.o
    CC         devices/pcix_device.ramstage.o
    CC         devices/pciexp_device.ramstage.o
    CC         devices/agp_device.ramstage.o
    CC         devices/cardbus_device.ramstage.o
    CC         devices/pnp_device.ramstage.o
    CC         devices/pci_ops.ramstage.o
    CC         devices/smbus_ops.ramstage.o
    CC         devices/pci_rom.ramstage.o
    CC         mainboard/emulation/qemu-x86/mainboard.ramstage.o
    CC         mainboard/emulation/qemu-x86/irq_tables.ramstage.o
    CC         mainboard/emulation/qemu-x86/northbridge.ramstage.o
    CC         pc80/mc146818rtc.ramstage.o
    CC         pc80/isa-dma.ramstage.o
    CC         pc80/i8259.ramstage.o
    CC         pc80/udelay_io.ramstage.o
    CC         pc80/keyboard.ramstage.o
    CC         devices/oprom/x86.ramstage.o
    CC         devices/oprom/x86_asm.ramstage.o
    CC         devices/oprom/x86_interrupts.ramstage.o
    CC         arch/x86/boot/boot.ramstage.o
    CC         arch/x86/boot/coreboot_table.ramstage.o
    CC         arch/x86/boot/multiboot.ramstage.o
    CC         arch/x86/boot/gdt.ramstage.o
    CC         arch/x86/boot/tables.ramstage.o
    CC         arch/x86/boot/pirq_routing.ramstage.o
    CC         arch/x86/lib/cpu.ramstage.o
    CC         arch/x86/lib/pci_ops_conf1.ramstage.o
    CC         arch/x86/lib/pci_ops_conf2.ramstage.o
    CC         arch/x86/lib/pci_ops_mmconf.ramstage.o
    CC         arch/x86/lib/pci_ops_auto.ramstage.o
    CC         arch/x86/lib/exception.ramstage.o
    CC         pc80/vga/vga_io.ramstage.o
    AR         coreboot.a
    CC         coreboot_ram.o
    CC         coreboot_ram
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards
(from 0000000000118000 to 0000000000004000)
collect2: ld returned 1 exit status
make: *** [build/coreboot_ram] Error 1

Thanks,

Hi,

You need to use our cross-compiler. Run 'make crossgcc' in the
coreboot directory and you will get our reference toolchain compiled.
Then run 'make' once again and everything should compile.

I will try to fix the doc if this is missing from there.

Cristi

Am Montag, den 20.06.2011, 15:19 -0700 schrieb Darren Hart:
> I'm new to coreboot

Welcome!

> and just trying to get it to boot into qemu. I've
> tried using SeaBios as well as just copying "yes" to payload.elf. I
> updated the Makefile to use gcc 4.5 instead of the 4.4 that ships with
> my distribution (Ubuntu 10.10):

[…]

> src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards
> (from 0000000000118000 to 0000000000004000)
> collect2: ld returned 1 exit status
> make: *** [build/coreboot_ram] Error 1

You should try the tested tool chain crossgcc [1].

        make crossgcc

which should be doing something similar as the following [2].

        cd coreboot/util/crossgcc 
        ./buildgcc 
        cd ../.. 
        rm -f .xcompile


Thanks,

Paul


[1] http://patchwork.coreboot.org/patch/2964/
[2] http://www.taringa.net/comunidades/linuxeros-debian/2899363/[Tutorial]+Compilar+coreboot.html

Hi Darren,

* Darren Hart <dvhart@linux.intel.com> [110621 00:19]:
> I'm new to coreboot and just trying to get it to boot into qemu. I've
> tried using SeaBios as well as just copying "yes" to payload.elf. I
> updated the Makefile to use gcc 4.5 instead of the 4.4 that ships with
> my distribution (Ubuntu 10.10):
 
> Index: Makefile
> ===================================================================
> --- Makefile	(revision 6637)
> +++ Makefile	(working copy)
> @@ -64,7 +64,7 @@
>  endif
>  endif
> 
> -HOSTCC = gcc
> +HOSTCC = gcc-4.5
>  HOSTCXX = g++
>  HOSTCFLAGS := -I$(srck) -I$(objk) -g
>  HOSTCXXFLAGS := -I$(srck) -I$(objk)

This will only change the compiler used to compile your userland
utilities. You need to change the script util/xcompile/xcompile to get
the target compiler changed. (And possibly delete the file .xcompile in
your coreboot directory before trying again)

>     CC         coreboot_ram
> src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards
> (from 0000000000118000 to 0000000000004000)
> collect2: ld returned 1 exit status
> make: *** [build/coreboot_ram] Error 1

This is a common tool chain bug we hit mostly on Ubuntu based systems so
far. (Maybe someone could open a bug report so they know about this
breakage?)

So far, the easiest way to get a known good toolchain is to build the
coreboot reference toolchain. It should build out of the box on any
Linux, MacOSX (with Xcode and MacPorts installed) and Windows (with
MINGW or Cygwin installed) system. To build it, go to util/crossgcc in
your coreboot tree and run the buildgcc script:

$ ./buildgcc

Then sit back and wait for a few minutes for the build to finish.

The resulting toolchain will per default end up in util/crossgcc/xgcc
and will be automatically picked up by the coreboot build system. Again,
you should delete your coreboot/.xcompile file after making changes to
the toolchain.

Hope that helps,

Stefan

Hi,

I documented the latest developments (git and crossgcc) at
http://www.coreboot.org/Build_HOWTO. Please someone double-check.

Cristi

On 06/20/2011 04:09 PM, Cristian Măgherușan-Stanciu wrote:
> Hi,
> 
> I documented the latest developments (git and crossgcc) at
> http://www.coreboot.org/Build_HOWTO. Please someone double-check.

My build succeeded following these instructions. As a first-time user,
it would be helpful to have a quick-start guide which would be basically
this wiki page + the steps necessary to do boot what I built in qemu.
There are bits of that here:

http://www.coreboot.org/QEMU

So perhaps a link, although it is a bit unclear to me which bits of what
I built get used when I try to boot searbios in qemu. I don't seem to
need corebios.rom at all, just the seabios bios.bin:

$ qemu -bios ./payloads/external/SeaBIOS/seabios/out/bios.bin -hda
/dev/zero -serial stdio

I get an option to press F12 in the console and select a boot device.
Seems to work.

Am I using coreboot? Is it integrated into the payload? Reading the
QEMU_Build_tutorial, http://www.coreboot.org/QEMU_Build_Tutorial, led me
to try:

$ qemu -bios build/coreboot.rom -hda /dev/zero -serial stdio

This resulted in something else entirely, the shell output terminating
in the following:

coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-0000000017feffff: RAM
 3. 0000000017ff0000-0000000017ffffff: CONFIGURATION TABLES
 4. 00000000ff800000-00000000ffffffff: RESERVED
Wrote coreboot table at: 17ff1400 - 17ff15c4  checksum 6c1c
coreboot table: 452 bytes.
Multiboot Information structure has been written.
 0. FREE SPACE 17ff3400 0000cc00
 1. GDT        17ff0200 00000200
 2. IRQ TABLE  17ff0400 00001000
 3. COREBOOT   17ff1400 00002000
Check CBFS header at fffcfc39
magic is 386f92fa
ERROR: No valid CBFS header found!
CBFS:  Could not find file fallback/payload
Boot failed.

It isn't clear to me from the various pages I've read which of the above
(if either) is the appropriate way to boot coreboot on qemu. Can anyone
clear that up for me?