From patchwork Thu Oct  1 20:44:18 2009
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Subject: update from revision guide for fam 0fh
Date: Thu, 01 Oct 2009 20:44:18 -0000
From: Rudolf Marek <r.marek@assembler.cz>
X-Patchwork-Id: 319
Message-Id: <4AC514A2.6050108@assembler.cz>
To: Coreboot <coreboot@coreboot.org>

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Hi all,

New revision guide September 2009 3.46
Lets add some more CPUs.

I also checked the Errata which we dont handle:

89, 169, 254,  292, (238 no resume?)

284, 325 (no resume?), 342 requires mcode.

Btw where to get the microcode for the fam 0fh?

here seems to be just for fam10h

http://www.amd64.org/support/microcode.html


Signed-off-by: Rudolf Marek <r.marek@assembler.cz>

(compile tested)

Rudolf
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Acked-by: Peter Stuge <peter@stuge.se>


Index: src/cpu/amd/model_fxx/processor_name.c
===================================================================
--- src/cpu/amd/model_fxx/processor_name.c	(revision 4704)
+++ src/cpu/amd/model_fxx/processor_name.c	(working copy)
@@ -302,6 +302,10 @@
 			processor_name_string =
 			    "AMD Athlon(tm) Neo Processor MV-TT";
 			break;
+		case 0x300c2:
+			processor_name_string =
+			    "AMD Sempron(tm) Processor 2RRU";
+			break;
 		/* dual-core */
 		case 0x31016:
 			processor_name_string =
@@ -352,6 +356,16 @@
 			processor_name_string =
 			    "AMD Athlon(tm) X2 Dual Core Processor TT50e";
 			break;
+		case 0x310a1:
+		case 0x310a2:
+			processor_name_string =
+			    "AMD Athlon(tm) Neo X2 Dual Core Processor TT50e";
+			break;
+		case 0x310b0:
+		case 0x310c0:
+			processor_name_string =
+			    "AMD Turion(tm) Neo X2 Dual Core Processor L6RR";
+			break;
 		/* Socket S1g1 */
 		/* single core */
 		case 0x00012:
@@ -384,6 +398,10 @@
 			processor_name_string =
 			    "AMD Athlon(tm) Processor TF-TT";
 			break;
+		case 0x00073:
+			processor_name_string =
+			    "AMD Athlon(tm) Processor L1RR";
+			break;
 		/* dual-core */
 		case 0x0101c:
 			processor_name_string =
@@ -402,6 +420,14 @@
 			processor_name_string =
 			    "AMD Athlon(tm) 64 X2 Dual Core Processor TT00+";
 			break;
+		case 0x01062:
+			processor_name_string =
+			    "AMD Athlon(tm) X2 Dual Core Processor L3RR";
+			break;
+		case 0x01074:
+			processor_name_string =
+			    "AMD Athlon(tm) X2 Dual Core Processor L5RR";
+			break;
 		default:
 			processor_name_string = "AMD Processor model unknown";
 		}
Index: src/cpu/amd/model_fxx/model_fxx_init.c
===================================================================
--- src/cpu/amd/model_fxx/model_fxx_init.c	(revision 4704)
+++ src/cpu/amd/model_fxx/model_fxx_init.c	(working copy)
@@ -631,6 +631,7 @@
 	{ X86_VENDOR_AMD, 0x40fc2 }, /* DH-F2 (socket S1g1) */
 	{ X86_VENDOR_AMD, 0x40f13 }, /* JH-F3 (socket F/1207) */
 	{ X86_VENDOR_AMD, 0x40f33 }, /* JH-F3 (socket AM2) */
+	{ X86_VENDOR_AMD, 0x50fd3 }, /* JH-F3 (socket F/1207) */
 	{ X86_VENDOR_AMD, 0xc0f13 }, /* JH-F3 (socket F/1207) */
 	{ X86_VENDOR_AMD, 0x50ff3 }, /* DH-F3 (socket AM2) */
 	{ X86_VENDOR_AMD, 0x60fb1 }, /* BH-G1 (socket AM2) */
@@ -639,6 +640,7 @@
 	{ X86_VENDOR_AMD, 0x60f82 }, /* BH-G2 (socket S1g1) */
 	{ X86_VENDOR_AMD, 0x70ff1 }, /* DH-G1 (socket AM2) */
 	{ X86_VENDOR_AMD, 0x60ff2 }, /* DH-G2 (socket AM2) */
+	{ X86_VENDOR_AMD, 0x70ff2 }, /* DH-G2 (socket AM2) */
 	{ X86_VENDOR_AMD, 0x60fc2 }, /* DH-G2 (socket S1g1) */
 	{ X86_VENDOR_AMD, 0x70fc2 }, /* DH-G2 (socket S1g1) */
 #endif