Patchwork AMD - SP5100 - take SPI ownership (2/2)

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Submitter Frederic Temporelli
Date 2011-08-01 08:47:43
Message ID <OF05B795B3.3A75E83D-ONC12578DF.003050A3-C12578DF.003050BA@bull.net>
Download mbox | patch
Permalink /patch/3323/
State Superseded
Headers show

Comments

Frederic Temporelli - 2011-08-01 08:47:43
Hello,


Here's the second patch that will remove the write protection.
If this patch isn't applied, even if SPI owenrship is ok, flashrom won't be able to write BIOS

Best regards

--
Fred
Thomas Gstädtner - 2011-10-19 21:20:45
On -10.01.-28163 20:59, Frederic Temporelli wrote:
> Hello,
> 
> 
> Here's the second patch that will remove the write protection.
> If this patch isn't applied, even if SPI owenrship is ok, flashrom won't be able to write BIOS
> 
> Best regards
> 
> ---
> Fred
> 
> diff -ur ../flashrom-0.9.4-r1394-sp5100/sb600spi.c ./sb600spi.c
> --- ../flashrom-0.9.4-r1394-sp5100/sb600spi.c	2011-07-29 22:45:48.693159918 -0400
> +++ ./sb600spi.c	2011-08-01 12:39:31.043163924 -0400
> @@ -381,23 +381,7 @@
>  		return 0;
>  	}
>  
> -	reg = pci_read_byte(dev, 0x40);
> -	msg_pdbg("SB700 IMC is %sactive.\n", (reg & (1 << 7)) ? "" : "not ");
> -	if (reg & (1 << 7)) {
> -		/* If we touch any region used by the IMC, the IMC and the SPI
> -		 * interface will lock up, and the only way to recover is a
> -		 * hard reset, but that is a bad choice for a half-erased or
> -		 * half-written flash chip.
> -		 * There appears to be an undocumented register which can freeze
> -		 * or disable the IMC, but for now we want to play it safe.
> -		 */
> -		msg_perr("The SB700 IMC is active and may interfere with SPI "
> -			 "commands. Disabling write.\n");
> -		/* FIXME: Should we only disable SPI writes, or will the lockup
> -		 * affect LPC/FWH chips as well?
> -		 */
> -		programmer_may_write = 0;
> -	}
> +	programmer_may_write = 1;
>  
>  	/* Bring the FIFO to a clean state. */
>  	reset_internal_fifo_pointer();

Acked-by: Thomas Gstaedtner <thomas@gstaedtner.net>

I tested this patch (along with 1/2 of course) on live hardware (>10
reads, >10 erase/writes) and it works fine for me.
Tested on: Supermicro H8SCM-F-O, AMD SP5100

Please note, that I did no proper code review, I only tested, so let me
know if the "acked-by" sign-off should not be used here.
It did not seem like you used the Tested-by sign-off.

thomasg

Patch

diff -ur ../flashrom-0.9.4-r1394-sp5100/sb600spi.c ./sb600spi.c
--- ../flashrom-0.9.4-r1394-sp5100/sb600spi.c	2011-07-29 22:45:48.693159918 -0400
+++ ./sb600spi.c	2011-08-01 12:39:31.043163924 -0400
@@ -381,23 +381,7 @@ 
 		return 0;
 	}
 
-	reg = pci_read_byte(dev, 0x40);
-	msg_pdbg("SB700 IMC is %sactive.\n", (reg & (1 << 7)) ? "" : "not ");
-	if (reg & (1 << 7)) {
-		/* If we touch any region used by the IMC, the IMC and the SPI
-		 * interface will lock up, and the only way to recover is a
-		 * hard reset, but that is a bad choice for a half-erased or
-		 * half-written flash chip.
-		 * There appears to be an undocumented register which can freeze
-		 * or disable the IMC, but for now we want to play it safe.
-		 */
-		msg_perr("The SB700 IMC is active and may interfere with SPI "
-			 "commands. Disabling write.\n");
-		/* FIXME: Should we only disable SPI writes, or will the lockup
-		 * affect LPC/FWH chips as well?
-		 */
-		programmer_may_write = 0;
-	}
+	programmer_may_write = 1;
 
 	/* Bring the FIFO to a clean state. */
 	reset_internal_fifo_pointer();