Patchwork CBFS issues on 440BX boards

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Submitter Uwe Hermann
Date 2009-10-04 23:13:28
Message ID <20091004231328.GB14135@greenwood>
Download mbox | patch
Permalink /patch/333/
State Accepted
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Comments

Uwe Hermann - 2009-10-04 23:13:28
On Sun, Oct 04, 2009 at 08:26:17PM +0200, Patrick Georgi wrote:
> Am Sonntag, den 04.10.2009, 20:08 +0200 schrieb Uwe Hermann:
> > Uncompressing coreboot to RAM.                                                  
> > Jumping to image.                                                               
> > Check CBFS header at fffedfe0                                                   
> > magic is ffffffff                                                               
> > ERROR: No valid CBFS header found!                                              
> > CBFS:  Could not find file fallback/coreboot_ram                                
> > Jumping to image.                                                               
[...] 
> A magic of 0xffffffff is suspicious, are you sure the ROM is entirely
> mapped before coreboot_ram is loaded?

That was indeed the problem, thanks!

We need to check for all chipsets and boards that full ROM access is
enabled very early (before any CBFS header parsing), e.g. right after
serial port init.

The attached patch does that for all 440BX boards.


Uwe.
Patrick Georgi - 2009-10-04 23:18:02
Am Montag, den 05.10.2009, 01:13 +0200 schrieb Uwe Hermann:
> We need to check for all chipsets and boards that full ROM access is
> enabled very early (before any CBFS header parsing), e.g. right after
> serial port init.
> 
> The attached patch does that for all 440BX boards.
Thank you for your effort!

Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Uwe Hermann - 2009-10-04 23:50:27
On Mon, Oct 05, 2009 at 01:18:02AM +0200, Patrick Georgi wrote:
> Am Montag, den 05.10.2009, 01:13 +0200 schrieb Uwe Hermann:
> > We need to check for all chipsets and boards that full ROM access is
> > enabled very early (before any CBFS header parsing), e.g. right after
> > serial port init.
> > 
> > The attached patch does that for all 440BX boards.
> Thank you for your effort!
> 
> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>

Thanks, r4721.


Uwe.

Patch

The new CBFS based build system requires the whole ROM to be accessible
in very early stages, otherwise the boot may hang like this because
the CBFS headers cannot be found/accessed:

  Uncompressing coreboot to RAM.
  Jumping to image.
  Check CBFS header at fffedfe0
  magic is ffffffff
  ERROR: No valid CBFS header found!
  CBFS:  Could not find file fallback/coreboot_ram
  Jumping to image.

This patch enables full ROM access on all 440BX boards right after the
serial init (and before CBFS headers are parsed).

Build-tested and runtime-tested on ASUS P2B-F.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>

Index: src/southbridge/intel/i82371eb/i82371eb_isa.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_isa.c	(Revision 4720)
+++ src/southbridge/intel/i82371eb/i82371eb_isa.c	(Arbeitskopie)
@@ -35,14 +35,6 @@ 
 	/* Initialize the real time clock (RTC). */
 	rtc_init(0);
 
-	/* Enable access to all BIOS regions. */
-	reg16 = pci_read_config16(dev, XBCS);
-	reg16 |= LOWER_BIOS_ENABLE;
-	reg16 |= EXT_BIOS_ENABLE;
-	reg16 |= EXT_BIOS_ENABLE_1MB;
-	reg16 &= ~(WRITE_PROTECT_ENABLE);	/* Disable ROM write access. */
-	pci_write_config16(dev, XBCS, reg16);
-
 	/*
 	 * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
 	 * bus, which is a subset of ISA. We select the full ISA bus here.
Index: src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_enable_rom.c	(Revision 0)
+++ src/southbridge/intel/i82371eb/i82371eb_enable_rom.c	(Revision 0)
@@ -0,0 +1,35 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include "i82371eb.h"
+
+static void i82371eb_enable_rom(device_t dev)
+{
+	u16 reg16;
+
+	/* Enable access to the whole ROM, disable ROM write access. */
+	reg16 = pci_read_config16(dev, XBCS);
+	reg16 |= LOWER_BIOS_ENABLE;
+	reg16 |= EXT_BIOS_ENABLE;
+	reg16 |= EXT_BIOS_ENABLE_1MB;
+	reg16 &= ~(WRITE_PROTECT_ENABLE);	/* Disable ROM write access. */
+	pci_write_config16(dev, XBCS, reg16);
+}
Index: src/mainboard/soyo/sy-6ba-plus-iii/auto.c
===================================================================
--- src/mainboard/soyo/sy-6ba-plus-iii/auto.c	(Revision 4720)
+++ src/mainboard/soyo/sy-6ba-plus-iii/auto.c	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
Index: src/mainboard/a-trend/atc-6240/auto.c
===================================================================
--- src/mainboard/a-trend/atc-6240/auto.c	(Revision 4720)
+++ src/mainboard/a-trend/atc-6240/auto.c	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
Index: src/mainboard/a-trend/atc-6220/auto.c
===================================================================
--- src/mainboard/a-trend/atc-6220/auto.c	(Revision 4720)
+++ src/mainboard/a-trend/atc-6220/auto.c	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
Index: src/mainboard/gigabyte/ga-6bxc/auto.c
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/auto.c	(Revision 4720)
+++ src/mainboard/gigabyte/ga-6bxc/auto.c	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
Index: src/mainboard/biostar/m6tba/auto.c
===================================================================
--- src/mainboard/biostar/m6tba/auto.c	(Revision 4720)
+++ src/mainboard/biostar/m6tba/auto.c	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -59,6 +60,10 @@ 
 	console_init();
 	report_bist_failure(bist);
 	enable_smbus();
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
 	/* dump_spd_registers(); */
 	sdram_set_registers();
 	sdram_set_spd_registers();
Index: src/mainboard/azza/pt-6ibd/auto.c
===================================================================
--- src/mainboard/azza/pt-6ibd/auto.c	(Revision 4720)
+++ src/mainboard/azza/pt-6ibd/auto.c	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
Index: src/mainboard/tyan/s1846/auto.c
===================================================================
--- src/mainboard/tyan/s1846/auto.c	(Revision 4720)
+++ src/mainboard/tyan/s1846/auto.c	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
Index: src/mainboard/abit/be6-ii_v2_0/auto.c
===================================================================
--- src/mainboard/abit/be6-ii_v2_0/auto.c	(Revision 4720)
+++ src/mainboard/abit/be6-ii_v2_0/auto.c	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge at 00:07.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
Index: src/mainboard/compaq/deskpro_en_sff_p600/auto.c
===================================================================
--- src/mainboard/compaq/deskpro_en_sff_p600/auto.c	(Revision 4720)
+++ src/mainboard/compaq/deskpro_en_sff_p600/auto.c	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 14, 0)); /* ISA bridge is 00:14.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
Index: src/mainboard/msi/ms6119/auto.c
===================================================================
--- src/mainboard/msi/ms6119/auto.c	(Revision 4720)
+++ src/mainboard/msi/ms6119/auto.c	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
Index: src/mainboard/msi/ms6147/auto.c
===================================================================
--- src/mainboard/msi/ms6147/auto.c	(Revision 4720)
+++ src/mainboard/msi/ms6147/auto.c	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
Index: src/mainboard/asus/p2b/auto.c
===================================================================
--- src/mainboard/asus/p2b/auto.c	(Revision 4720)
+++ src/mainboard/asus/p2b/auto.c	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
Index: src/mainboard/asus/p2b-d/auto.c
===================================================================
--- src/mainboard/asus/p2b-d/auto.c	(Revision 4720)
+++ src/mainboard/asus/p2b-d/auto.c	(Arbeitskopie)
@@ -31,6 +31,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
Index: src/mainboard/asus/p2b-f/auto.c
===================================================================
--- src/mainboard/asus/p2b-f/auto.c	(Revision 4720)
+++ src/mainboard/asus/p2b-f/auto.c	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
Index: src/mainboard/asus/p2b-ds/auto.c
===================================================================
--- src/mainboard/asus/p2b-ds/auto.c	(Revision 4720)
+++ src/mainboard/asus/p2b-ds/auto.c	(Arbeitskopie)
@@ -31,6 +31,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();
Index: src/mainboard/asus/p3b-f/auto.c
===================================================================
--- src/mainboard/asus/p3b-f/auto.c	(Revision 4720)
+++ src/mainboard/asus/p3b-f/auto.c	(Arbeitskopie)
@@ -30,6 +30,7 @@ 
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ 
 	uart_init();
 	console_init();
 	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
 	enable_smbus();
 	/* dump_spd_registers(); */
 	sdram_set_registers();