Patchwork Error out when chipset/board doesn't decode full ROM

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Submitter Uwe Hermann
Date 2009-10-06 11:52:03
Message ID <20091006115203.GB17757@greenwood>
Download mbox | patch
Permalink /patch/349/
State Superseded
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Comments

Uwe Hermann - 2009-10-06 11:52:03
See patch.

I'm thankful for better suggestions to track which chipsets and
especially boards can decode how much.

For boards we need to autodetect them (not possible for all boards
unfortunately). For those with board-enables we could reuse that
table and enhance/add board-enables, whether that's a good idea
is another issue.

For boards that cannot be autodetected we should at least have a table
of the max. supported ROM chip size, which can be printed in
"flashrom -L" and in the wiki.


Uwe.
Carl-Daniel Hailfinger - 2009-10-23 01:04:43
On 06.10.2009 13:52, Uwe Hermann wrote:
> I'm thankful for better suggestions to track which chipsets and
> especially boards can decode how much.
>   

Could you please change chipset_max_rom_decode_kb to a struct with one
value per bustype? All Intel chipsets with SPI support have two
independent limits: One for FWH and one for SPI. SB600 has three limits:
FWH, LPC and SPI (yes, it can speak FWH).


> For boards we need to autodetect them (not possible for all boards
> unfortunately). For those with board-enables we could reuse that
> table and enhance/add board-enables, whether that's a good idea
> is another issue.
>   

Board matching is already done via board enables. While the size limit
is not directly a board enable, we also use board enables to add buses
(e.g. behind a IT8716F SPI), so it would only be logical to use board
enables for board sizing constraints.

How should we handle double limits (board+chipset)? Pick the minimum?
Logical AND?

IMHO the chipset enable should set the limits for every supported bus,
and the board enable should override settings where/how appropriate.
That also means there's only one variable per bus. If you change your
patch that way, I think I'll ack it right away.


> For boards that cannot be autodetected we should at least have a table
> of the max. supported ROM chip size, which can be printed in
> "flashrom -L" and in the wiki.
>   

Such boards will appear as "needs special board enable", though. Oh
well. Maybe it is time to introduce a "reason" bitfield in the board
enable table which says why the board is listed there.

Regards,
Carl-Daniel

Patch

Add a facility to check and report to the user the maximum supported
decode size for (a) chipsets and (c) tested mainboards.

The rationale is to warn users when they, for example, try to flash
a 512KB parallel flash chip but their chipset only supports 256KB,
or they try to flash 512KB and the chipset _does_ theoretically
support 512KB but their special board doesn't wire all address lines
and thus supports only 256 KB ROM chips at maximum.

This has costed me hours of debugging on some board already, until I
figured out what was going on, we should try warn our users where
possible about this (yes, this is "best effort", but still better than
not to warn at all).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>

Index: flash.h
===================================================================
--- flash.h	(Revision 747)
+++ flash.h	(Arbeitskopie)
@@ -344,6 +344,8 @@ 
 void print_supported_pcidevs(struct pcidev_status *devs);
 void print_wiki_tables(void);
 
+#define ROM_DECODE_SIZE_UNKNOWN 0xffffffff
+
 /* board_enable.c */
 void w836xx_ext_enter(uint16_t port);
 void w836xx_ext_leave(uint16_t port);
@@ -351,10 +353,12 @@ 
 void sio_write(uint16_t port, uint8_t reg, uint8_t data);
 void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
 int board_flash_enable(const char *vendor, const char *part);
+extern uint32_t board_max_rom_decode_kb;
 
 /* chipset_enable.c */
 extern enum chipbustype buses_supported;
 int chipset_flash_enable(void);
+extern uint32_t chipset_max_rom_decode_kb;
 
 extern unsigned long flashbase;
 
Index: chipset_enable.c
===================================================================
--- chipset_enable.c	(Revision 747)
+++ chipset_enable.c	(Arbeitskopie)
@@ -41,6 +41,7 @@ 
  */
 
 enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI;
+uint32_t chipset_max_rom_decode_kb = ROM_DECODE_SIZE_UNKNOWN;
 
 extern int ichspi_lock;
 
@@ -536,6 +537,8 @@ 
 	reg8 |= BIOS_ROM_POSITIVE_DECODE;
 	pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
 
+	chipset_max_rom_decode_kb = 256;
+
 	return 0;
 }
 
@@ -1021,9 +1024,8 @@ 
 	{0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4",  enable_flash_nvidia_nforce2},
 	{0x10de, 0x0050, OK, "NVIDIA", "CK804",		enable_flash_ck804}, /* LPC */
 	{0x10de, 0x0051, OK, "NVIDIA", "CK804",		enable_flash_ck804}, /* Pro */
-	{0x10de, 0x0060, OK, "NVIDIA", "NForce2",       enable_flash_nvidia_nforce2},
-	/* Slave, should not be here, to fix known bug for A01. */
-	{0x10de, 0x00d3, OK, "NVIDIA", "CK804",		enable_flash_ck804},
+	{0x10de, 0x0060, OK, "NVIDIA", "NForce2",	enable_flash_nvidia_nforce2},
+	{0x10de, 0x00d3, OK, "NVIDIA", "CK804",		enable_flash_ck804}, /* Slave, should not be here, to fix known bug for A01. */
 	{0x10de, 0x0260, NT, "NVIDIA", "MCP51",		enable_flash_ck804},
 	{0x10de, 0x0261, NT, "NVIDIA", "MCP51",		enable_flash_ck804},
 	{0x10de, 0x0262, NT, "NVIDIA", "MCP51",		enable_flash_ck804},
Index: flashrom.c
===================================================================
--- flashrom.c	(Revision 747)
+++ flashrom.c	(Arbeitskopie)
@@ -977,6 +977,13 @@ 
 	size = flash->total_size * 1024;
 	buf = (uint8_t *) calloc(size, sizeof(char));
 
+	if (board_max_rom_decode_kb != ROM_DECODE_SIZE_UNKNOWN) {
+		fprintf(stderr, "ERROR: The biggest ROM chip supported in "
+		       "this board is %d KB.", board_max_rom_decode_kb);
+		programmer_shutdown();
+		exit(1);
+	}
+
 	if (erase_it) {
 		if (flash->tested & TEST_BAD_ERASE) {
 			fprintf(stderr, "Erase is not working on this chip. ");
Index: board_enable.c
===================================================================
--- board_enable.c	(Revision 747)
+++ board_enable.c	(Arbeitskopie)
@@ -28,6 +28,8 @@ 
 #include <fcntl.h>
 #include "flash.h"
 
+uint32_t board_max_rom_decode_kb = ROM_DECODE_SIZE_UNKNOWN;
+
 /*
  * Helper functions for many Winbond Super I/Os of the W836xx range.
  */
@@ -783,17 +785,30 @@ 
 	return 0;
 }
 
-/**
- * Suited for:
- *   - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F
- *   - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F
- */
 static int it8705f_write_enable_2e(const char *name)
 {
 	return it8705f_write_enable(0x2e, name);
 }
 
 /**
+ * Suited for: Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F
+ */
+static int elitegroup_k7vta3(const char *name)
+{
+	board_max_rom_decode_kb = 256;
+	return it8705f_write_enable_2e(name);
+}
+
+/**
+ * Suited for: Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F
+ */
+static int shuttle_ak38n(const char *name)
+{
+	board_max_rom_decode_kb = 256;
+	return it8705f_write_enable_2e(name);
+}
+
+/**
  * Find the runtime registers of an SMSC Super I/O, after verifying its
  * chip ID.
  *
@@ -1053,7 +1068,7 @@ 
 	{0x10DE, 0x0030, 0x1043, 0x818a,  0x8086, 0x100E, 0x1043, 0x80EE, NULL,         NULL,          "ASUS",        "P5ND2-SLI Deluxe",   board_asus_p5nd2_sli},
 	{0x1106, 0x3149, 0x1565, 0x3206,  0x1106, 0x3344, 0x1565, 0x1202, NULL,         NULL,          "Biostar",     "P4M80-M4",           it8705_rom_write_enable},
 	{0x8086, 0x3590, 0x1028, 0x016c,  0x1000, 0x0030, 0x1028, 0x016c, NULL,         NULL,          "Dell",        "S1850",              ich5_gpio23_raise},
-	{0x1106, 0x3038, 0x1019, 0x0996,  0x1106, 0x3177, 0x1019, 0x0996, NULL,         NULL,          "Elitegroup",  "K7VTA3",             it8705f_write_enable_2e},
+	{0x1106, 0x3038, 0x1019, 0x0996,  0x1106, 0x3177, 0x1019, 0x0996, NULL,         NULL,          "Elitegroup",  "K7VTA3",             elitegroup_k7vta3},
 	{0x1106, 0x3177, 0x1106, 0x3177,  0x1106, 0x3059, 0x1695, 0x3005, NULL,         NULL,          "EPoX",        "EP-8K5A2",           board_epox_ep_8k5a2},
 	{0x10EC, 0x8139, 0x1695, 0x9001,  0x11C1, 0x5811, 0x1695, 0x9015, NULL,         NULL,          "EPoX",        "EP-8RDA3+",          board_epox_ep_8rda3plus},
 	{0x8086, 0x7110,      0,      0,  0x8086, 0x7190,      0,      0, "epox",       "ep-bx3",      "EPoX",        "EP-BX3",             board_epox_ep_bx3},
@@ -1079,7 +1094,7 @@ 
 	{0x1106, 0x0571, 0x1462, 0x7120,       0,      0,      0,      0, "msi",        "kt4v",        "MSI",         "MS-6712 (KT4V)",     board_msi_kt4v},
 	{0x8086, 0x2658, 0x1462, 0x7046,  0x1106, 0x3044, 0x1462, 0x046d, NULL,         NULL,          "MSI",         "MS-7046",            ich6_gpio19_raise},
 	{0x10de, 0x005e,      0,      0,       0,      0,      0,      0, "msi",        "k8n-neo3",    "MSI",         "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e},
-	{0x1106, 0x3104, 0x1297, 0xa238,  0x1106, 0x3059, 0x1297, 0xc063, NULL,         NULL,          "Shuttle",     "AK38N",              it8705f_write_enable_2e},
+	{0x1106, 0x3104, 0x1297, 0xa238,  0x1106, 0x3059, 0x1297, 0xc063, NULL,         NULL,          "Shuttle",     "AK38N",              shuttle_ak38n},
 	{0x1106, 0x3038, 0x0925, 0x1234,  0x1106, 0x3058, 0x15DD, 0x7609, NULL,         NULL,          "Soyo",        "SY-7VCA",            board_soyo_sy_7vca},
 	{0x8086, 0x1076, 0x8086, 0x1176,  0x1106, 0x3059, 0x10f1, 0x2498, NULL,         NULL,          "Tyan",        "S2498 (Tomcat K7M)", board_asus_a7v8x_mx},
 	{0x1106, 0x0314, 0x1106, 0xaa08,  0x1106, 0x3227, 0x1106, 0xAA08, NULL,         NULL,          "VIA",         "EPIA-CN",            board_via_epia_sp},