Add early init for pc8374. I use a simple u8 * for the initialization value;
tried a struct but it did not work with romcc.
Other bug fixes and attempts for s1850. We're now configuring
memory, incorrectly.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
===================================================================
@@ -0,0 +1,27 @@
+#include <arch/romcc_io.h>
+#include "pc8374.h"
+
+/* things that Must Be Done to get this chip working */
+/* Straight from the data book */
+static void pc8374_enable(unsigned iobase, u8 *init)
+{
+ u8 val, count;
+ outb(0x29, iobase);
+ val = inb(iobase+1);
+ val |= 0x91;
+ outb(val, iobase+1);
+ for(count = 0; count < 255; count++)
+ if (inb(iobase+1) == 0x91)
+ break;
+ for(;*init; init++) {
+ outb(*init, iobase);
+ val = inb(iobase+1);
+ init++;
+ val &= *init;
+ init++;
+ val |= *init;
+ outb(val, iobase+1);
+ }
+
+
+}
Property changes on: src/superio/nsc/pc8374/pc8374_early_init.c
___________________________________________________________________
Added: svn:mergeinfo
===================================================================
@@ -13,6 +13,7 @@
#include "lib/ramtest.c"
#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
+#include "superio/nsc/pc8374/pc8374_early_init.c"
#include "superio/nsc/pc8374/pc8374_early_serial.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c"
@@ -65,6 +66,25 @@
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
+ /* fake it out for this board */
+ switch(device) {
+ case 0x52:
+ case 0x53:
+ print_debug("FAKE");
+ device = 0x50;
+ break;
+ case 0x50:
+ case 0x51:
+ case 0x54:
+ case 0x55:
+ case 0x56:
+ case 0x57:
+ print_debug("57");
+ device = 0x57;
+ break;
+ default:
+ die("BAD DEV IN spd_read_byte");
+ }
return smbus_read_byte(device, address);
}
@@ -191,11 +211,22 @@
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
- .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
- .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
+ .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
+ .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
}
};
+ /* superio setup */
+ /* observed from serialice */
+ static const u8 earlyinit[] = {
+ 0x21, 0x11, 0x11,
+ 0x22, 1, 1,
+ 0x23, 05, 05,
+ 0x24, 0x81, 0x81,
+ 0x26, 0, 0,
+ 0,
+ };
+
/* using SerialICE, we've seen this basic reset sequence on the dell.
* we don't understand it as it uses undocumented registers, but
* we're going to clone it.
@@ -261,10 +292,10 @@
pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
/* ?? */
- l = pci_read_config32(PCI_DEV(0, 0, 8), 0xc0);
+ l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0);
do_reset = l & 0x8000000;
l |= 0x8000000;
- pci_write_config32(PCI_DEV(0, 0, 2), 0xc0, l);
+ pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l);
if (! do_reset) {
outb(2, 0xcf9);
@@ -279,7 +310,7 @@
}
/* Setup the console */
mainboard_set_ich5();
- bmc_foad();
+ //bmc_foad();
pc8374_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -306,7 +337,7 @@
#if 1
enable_smbus();
#endif
-#if 1
+#if 0
// dump_spd_registers(&cpu[0]);
int i;
for(i = 0; i < 1; i++) {