Patchwork [AMD,Fam10] Fix confused RB-C2 and DA-C2

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Submitter Bao, Zheng
Date 2009-07-16 07:40:49
Message ID <DD1CC71B621B004FA76856E5129D6B1702DDC385@sbjgexmb1.amd.com>
Download mbox | patch
Permalink /patch/36/
State Accepted
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Comments

Bao, Zheng - 2009-07-16 07:40:49
This patch is about the DA-C2 and RB-C2. Chip with install processor
Revision ID of 0x100F62 is DA-C2, instead of RB-C2 which was incorrectly
defined in raminit_amdmct.c. RB-C2's ID is 0x100F42. The Erratas applied
to
them are almost the same.

Issues:
1. I really dont know what their nicknames are (Shanghai C2 or
something).
2. About the mc_patch_01000086.h, I dont know if it is allowed to be
released.
   If you really need it, please contact AMD Inc to see if it is public.
3. I haven't made coreboot go thoroughly on this RB-C2. This patch is
just half tested.
   I am not confident it is 100% correct.

Zheng


Signed-off-by: Zheng Bao <zheng.bao@amd.com>



\n"); <<amd_fam10_RBC2_DAC2_fix.patch>>
Ward Vandewege - 2009-07-16 14:36:39
Hi Zheng,

On Thu, Jul 16, 2009 at 03:40:49PM +0800, Bao, Zheng wrote:
> This patch is about the DA-C2 and RB-C2. Chip with install processor
> Revision ID of 0x100F62 is DA-C2, instead of RB-C2 which was incorrectly
> defined in raminit_amdmct.c. RB-C2's ID is 0x100F42. The Erratas applied
> to them are almost the same.

Aha. That would perhaps explain why my box with 

  Quad-Core AMD Opteron(tm) Processor 2372 HE

with revision id 0x100f42 really does not like ucode revision 92 (it resets
itself constantly).

> Issues:
> 1. I really dont know what their nicknames are (Shanghai C2 or
> something).

Don't know about that.

> 2. About the mc_patch_01000086.h, I dont know if it is allowed to be
> released.
>    If you really need it, please contact AMD Inc to see if it is public.

Well, I have my box booting without any ucode update. It would be nice to
have mc_patch_01000086.h public if that's the revision for my cpus. Who do I
ask?

> 3. I haven't made coreboot go thoroughly on this RB-C2. This patch is
> just half tested.

I now have a working tree for Supermicro h8dmr with RB-C2 but it needs a bit
more tweaking and cleaning up. I hope to get that ready soon so I can submit
the patch to the list.

>    I am not confident it is 100% correct.

I'll test tonight or tomorrow and let you know how it goes.

Thanks!
Ward.
Bao, Zheng - 2009-07-17 02:01:35
RB-C2 probably uses socket type AM3, which is not supported in Coreboot
currently. I wonder if your board can go through the whole image.

You can contact tim.perley@amd.com about the patch releasing.

Zheng

-----Original Message-----
From: Ward Vandewege [mailto:ward@gnu.org] 
Sent: Thursday, July 16, 2009 10:37 PM
To: Bao, Zheng
Cc: Coreboot
Subject: Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

Hi Zheng,

On Thu, Jul 16, 2009 at 03:40:49PM +0800, Bao, Zheng wrote:
> This patch is about the DA-C2 and RB-C2. Chip with install processor
> Revision ID of 0x100F62 is DA-C2, instead of RB-C2 which was
incorrectly
> defined in raminit_amdmct.c. RB-C2's ID is 0x100F42. The Erratas
applied
> to them are almost the same.

Aha. That would perhaps explain why my box with 

  Quad-Core AMD Opteron(tm) Processor 2372 HE

with revision id 0x100f42 really does not like ucode revision 92 (it
resets
itself constantly).

> Issues:
> 1. I really dont know what their nicknames are (Shanghai C2 or
> something).

Don't know about that.

> 2. About the mc_patch_01000086.h, I dont know if it is allowed to be
> released.
>    If you really need it, please contact AMD Inc to see if it is
public.

Well, I have my box booting without any ucode update. It would be nice
to
have mc_patch_01000086.h public if that's the revision for my cpus. Who
do I
ask?

> 3. I haven't made coreboot go thoroughly on this RB-C2. This patch is
> just half tested.

I now have a working tree for Supermicro h8dmr with RB-C2 but it needs a
bit
more tweaking and cleaning up. I hope to get that ready soon so I can
submit
the patch to the list.

>    I am not confident it is 100% correct.

I'll test tonight or tomorrow and let you know how it goes.

Thanks!
Ward.
Christian Leber - 2009-07-17 09:24:20
On Friday 17 July 2009 04:01:35 Bao, Zheng wrote:

Hi Zheng

> RB-C2 probably uses socket type AM3, which is not supported in Coreboot
> currently. I wonder if your board can go through the whole image.

The RB-C2 / 0x100f42 is socket F.


Christian
Bao, Zheng - 2009-07-17 09:45:22
Hi, Christian, 

In Fam10 BKDG, it says

CPUID Fn8000_0001_EBX BrandId Identifier
  Bits Description
31:28 PkgType: package type. Specifies the processor package type. 
         This field is encoded as follows:

0000b: Fr2(1207), Fr5(1207), or Fr6(1207). 
0001b: AM2r2 or AM3.
0010b: S1g3 or S1g4. 0011b: G34.
0100b: ASB2. 0101b: C32.

The CPUID Fn8000_0001_EBX of the CPU I am using is 0x10002056, whose bit
31:28 is 1, right?

Zheng

-----Original Message-----
From: Christian Leber [mailto:christian.leber@ziti.uni-heidelberg.de] 
Sent: Friday, July 17, 2009 5:24 PM
To: coreboot@coreboot.org
Cc: Bao, Zheng
Subject: Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

On Friday 17 July 2009 04:01:35 Bao, Zheng wrote:

Hi Zheng

> RB-C2 probably uses socket type AM3, which is not supported in
Coreboot
> currently. I wonder if your board can go through the whole image.

The RB-C2 / 0x100f42 is socket F.


Christian
Ward Vandewege - 2009-07-17 15:41:39
On Fri, Jul 17, 2009 at 10:01:35AM +0800, Bao, Zheng wrote:
> RB-C2 probably uses socket type AM3, which is not supported in Coreboot
> currently. I wonder if your board can go through the whole image.

Hmm, I think there is some confusion here. If RB-C2 is really 0x100F42, then
we are most certainly talking about Socket F. I have a few Opteron 2372 HE
CPUs that are 0x100F42.

> You can contact tim.perley@amd.com about the patch releasing.

Thank you, I have done so.

Thanks,
Ward.
Bao, Zheng - 2009-07-20 02:10:13
According to the Revision Guide, I think there might be several kinds of
0x100F42 RB-C2. They are AM2r2, AM3, F1207. The actual socket type
should be read from CPUID_80000001_EBX. Right?

Zheng

-----Original Message-----
From: Ward Vandewege [mailto:ward@gnu.org] 
Sent: Friday, July 17, 2009 11:42 PM
To: Bao, Zheng
Cc: Coreboot
Subject: Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

On Fri, Jul 17, 2009 at 10:01:35AM +0800, Bao, Zheng wrote:
> RB-C2 probably uses socket type AM3, which is not supported in
Coreboot
> currently. I wonder if your board can go through the whole image.

Hmm, I think there is some confusion here. If RB-C2 is really 0x100F42,
then
we are most certainly talking about Socket F. I have a few Opteron 2372
HE
CPUs that are 0x100F42.

> You can contact tim.perley@amd.com about the patch releasing.

Thank you, I have done so.

Thanks,
Ward.
Peter Stuge - 2009-07-20 18:59:19
Bao, Zheng wrote:
> In Fam10 BKDG, it says
> 
> 31:28 PkgType: package type. Specifies the processor package type. 
>          This field is encoded as follows:
> 
> 0001b: AM2r2 or AM3.

What is the difference between AM2 and AM2r2?


//Peter
Ward Vandewege - 2009-07-20 19:58:06
On Thu, Jul 16, 2009 at 03:40:49PM +0800, Bao, Zheng wrote:
> This patch is about the DA-C2 and RB-C2. Chip with install processor
> Revision ID of 0x100F62 is DA-C2, instead of RB-C2 which was incorrectly
> defined in raminit_amdmct.c. RB-C2's ID is 0x100F42. The Erratas applied
> to
> them are almost the same.
> 
> Issues:
> 1. I really dont know what their nicknames are (Shanghai C2 or
> something).
> 2. About the mc_patch_01000086.h, I dont know if it is allowed to be
> released.
>    If you really need it, please contact AMD Inc to see if it is public.
> 3. I haven't made coreboot go thoroughly on this RB-C2. This patch is
> just half tested.
>    I am not confident it is 100% correct.
> 
> Zheng
> 
> 
> Signed-off-by: Zheng Bao <zheng.bao@amd.com>

With this patch, I can still boot my system with 00100F42h (RB-C2) CPUs -
Opteron 2372HE.

Acked-by: Ward Vandewege <ward@gnu.org>

Thanks,
Ward.
Ward Vandewege - 2009-07-20 22:35:21
On Mon, Jul 20, 2009 at 10:10:13AM +0800, Bao, Zheng wrote:
> According to the Revision Guide, I think there might be several kinds of
> 0x100F42 RB-C2. They are AM2r2, AM3, F1207. 

Yeah, I see that on page 10 of the Fam10h Revision guide.

Note that the link on

  http://developer.amd.com/documentation/guides/Pages/default.aspx

to the Fam10 revision guide is wrong, the correct link is 

  http://support.amd.com/us/Processor_TechDocs/41322.pdf

> The actual socket type
> should be read from CPUID_80000001_EBX. Right?

I think so, according to the revision guide...

Thanks,
Ward.
Bao, Zheng - 2009-07-21 02:06:57
If anyone can tell me what the nicknames of AMD_RB_C2 & AMD_DA_C2 are, I
will submit the code.


Zheng

-----Original Message-----
From: Ward Vandewege [mailto:ward@gnu.org] 
Sent: Tuesday, July 21, 2009 3:58 AM
To: Bao, Zheng
Cc: Coreboot
Subject: Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

On Thu, Jul 16, 2009 at 03:40:49PM +0800, Bao, Zheng wrote:
> This patch is about the DA-C2 and RB-C2. Chip with install processor
> Revision ID of 0x100F62 is DA-C2, instead of RB-C2 which was
incorrectly
> defined in raminit_amdmct.c. RB-C2's ID is 0x100F42. The Erratas
applied
> to
> them are almost the same.
> 
> Issues:
> 1. I really dont know what their nicknames are (Shanghai C2 or
> something).
> 2. About the mc_patch_01000086.h, I dont know if it is allowed to be
> released.
>    If you really need it, please contact AMD Inc to see if it is
public.
> 3. I haven't made coreboot go thoroughly on this RB-C2. This patch is
> just half tested.
>    I am not confident it is 100% correct.
> 
> Zheng
> 
> 
> Signed-off-by: Zheng Bao <zheng.bao@amd.com>

With this patch, I can still boot my system with 00100F42h (RB-C2) CPUs
-
Opteron 2372HE.

Acked-by: Ward Vandewege <ward@gnu.org>

Thanks,
Ward.
Bao, Zheng - 2009-08-06 02:26:38
I am trying to port the ddr3 feature. I will submit a full patch to
replace this one.


Zheng

-----Original Message-----
From: Ward Vandewege [mailto:ward@gnu.org] 
Sent: Tuesday, July 21, 2009 3:58 AM
To: Bao, Zheng
Cc: Coreboot
Subject: Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

On Thu, Jul 16, 2009 at 03:40:49PM +0800, Bao, Zheng wrote:
> This patch is about the DA-C2 and RB-C2. Chip with install processor
> Revision ID of 0x100F62 is DA-C2, instead of RB-C2 which was
incorrectly
> defined in raminit_amdmct.c. RB-C2's ID is 0x100F42. The Erratas
applied
> to
> them are almost the same.
> 
> Issues:
> 1. I really dont know what their nicknames are (Shanghai C2 or
> something).
> 2. About the mc_patch_01000086.h, I dont know if it is allowed to be
> released.
>    If you really need it, please contact AMD Inc to see if it is
public.
> 3. I haven't made coreboot go thoroughly on this RB-C2. This patch is
> just half tested.
>    I am not confident it is 100% correct.
> 
> Zheng
> 
> 
> Signed-off-by: Zheng Bao <zheng.bao@amd.com>

With this patch, I can still boot my system with 00100F42h (RB-C2) CPUs
-
Opteron 2372HE.

Acked-by: Ward Vandewege <ward@gnu.org>

Thanks,
Ward.
Ward Vandewege - 2009-08-06 15:39:59
On Thu, Aug 06, 2009 at 10:26:38AM +0800, Bao, Zheng wrote:
> I am trying to port the ddr3 feature. I will submit a full patch to
> replace this one.

Sounds good, thanks. I won't be able to test until the end of August though,
but perhaps someone else can ack before then.

Thanks,
Ward.
Bao, Zheng - 2009-08-24 06:32:00
Committed to r4562.

-----Original Message-----
From: coreboot-bounces@coreboot.org
[mailto:coreboot-bounces@coreboot.org] On Behalf Of Bao, Zheng
Sent: Thursday, August 06, 2009 10:27 AM
To: Ward Vandewege
Cc: Coreboot
Subject: Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

I am trying to port the ddr3 feature. I will submit a full patch to
replace this one.


Zheng

-----Original Message-----
From: Ward Vandewege [mailto:ward@gnu.org] 
Sent: Tuesday, July 21, 2009 3:58 AM
To: Bao, Zheng
Cc: Coreboot
Subject: Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

On Thu, Jul 16, 2009 at 03:40:49PM +0800, Bao, Zheng wrote:
> This patch is about the DA-C2 and RB-C2. Chip with install processor
> Revision ID of 0x100F62 is DA-C2, instead of RB-C2 which was
incorrectly
> defined in raminit_amdmct.c. RB-C2's ID is 0x100F42. The Erratas
applied
> to
> them are almost the same.
> 
> Issues:
> 1. I really dont know what their nicknames are (Shanghai C2 or
> something).
> 2. About the mc_patch_01000086.h, I dont know if it is allowed to be
> released.
>    If you really need it, please contact AMD Inc to see if it is
public.
> 3. I haven't made coreboot go thoroughly on this RB-C2. This patch is
> just half tested.
>    I am not confident it is 100% correct.
> 
> Zheng
> 
> 
> Signed-off-by: Zheng Bao <zheng.bao@amd.com>

With this patch, I can still boot my system with 00100F42h (RB-C2) CPUs
-
Opteron 2372HE.

Acked-by: Ward Vandewege <ward@gnu.org>

Thanks,
Ward.
Bao, Zheng - 2009-08-24 08:14:43
Issues:
1. I really don't know what their nicknames are (Shanghai C2 or
something).
2. About the mc_patch_01000086.h, I don't know if it is allowed to be
released.  If you really need it, please contact AMD Inc to see if it is
public.
3. My RB-C2 is Socket type AM3, which needs DDR3 support. Probably your
RB-C2 doesn't need DDR3. If it does and you really need it, please
contact AMD Inc to see if it is allowed to release DDR3 code.

Zheng

-----Original Message-----
From: coreboot-bounces@coreboot.org
[mailto:coreboot-bounces@coreboot.org] On Behalf Of Bao, Zheng
Sent: Monday, August 24, 2009 2:32 PM
To: Coreboot
Subject: Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

Committed to r4562.

-----Original Message-----
From: coreboot-bounces@coreboot.org
[mailto:coreboot-bounces@coreboot.org] On Behalf Of Bao, Zheng
Sent: Thursday, August 06, 2009 10:27 AM
To: Ward Vandewege
Cc: Coreboot
Subject: Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

I am trying to port the ddr3 feature. I will submit a full patch to
replace this one.


Zheng

-----Original Message-----
From: Ward Vandewege [mailto:ward@gnu.org] 
Sent: Tuesday, July 21, 2009 3:58 AM
To: Bao, Zheng
Cc: Coreboot
Subject: Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

On Thu, Jul 16, 2009 at 03:40:49PM +0800, Bao, Zheng wrote:
> This patch is about the DA-C2 and RB-C2. Chip with install processor
> Revision ID of 0x100F62 is DA-C2, instead of RB-C2 which was
incorrectly
> defined in raminit_amdmct.c. RB-C2's ID is 0x100F42. The Erratas
applied
> to
> them are almost the same.
> 
> Issues:
> 1. I really dont know what their nicknames are (Shanghai C2 or
> something).
> 2. About the mc_patch_01000086.h, I dont know if it is allowed to be
> released.
>    If you really need it, please contact AMD Inc to see if it is
public.
> 3. I haven't made coreboot go thoroughly on this RB-C2. This patch is
> just half tested.
>    I am not confident it is 100% correct.
> 
> Zheng
> 
> 
> Signed-off-by: Zheng Bao <zheng.bao@amd.com>

With this patch, I can still boot my system with 00100F42h (RB-C2) CPUs
-
Opteron 2372HE.

Acked-by: Ward Vandewege <ward@gnu.org>

Thanks,
Ward.

Patch

Index: src/cpu/amd/model_10xxx/update_microcode.c
===================================================================
--- src/cpu/amd/model_10xxx/update_microcode.c	(revision 4426)
+++ src/cpu/amd/model_10xxx/update_microcode.c	(working copy)
@@ -44,6 +44,7 @@ 
  * 00100F2Ah (DR-BA)     1020h                  01000096h
  * 00100F22h (DR-B2)     1022h                  01000095h
  * 00100F23h (DR-B3)     1022h                  01000095h
+ * 00100F42h (RB-C2)     1041h                  01000086h
  * 00100F62h (DA-C2)     1062h                  0100009Fh
  */
 
@@ -67,6 +68,7 @@ 
 		0x100f2A, 0x1020,
 		0x100f22, 0x1022,
 		0x100f23, 0x1022,
+		0x100f42, 0x1041,
 		0x100f62, 0x1062,
 	};
 
Index: src/cpu/amd/model_10xxx/defaults.h
===================================================================
--- src/cpu/amd/model_10xxx/defaults.h	(revision 4426)
+++ src/cpu/amd/model_10xxx/defaults.h	(working copy)
@@ -290,7 +290,7 @@ 
 
 	/* errata 346 - Fam10 C2
 	 *  System software should set F3x188[22] to 1b. */
-	{ 3, 0x188, AMD_RB_C2, AMD_PTYPE_ALL,
+	{ 3, 0x188, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
 	  0x00400000, 0x00400000 },
 
 	/* L3 Control Register */
@@ -317,82 +317,82 @@ 
 
 	/* Errata 344 - Fam10 C2
 	 * System software should set bit 6 of F4x1[9C, 94, 8C,
84]_x[78:70, 68:60]. */
-	{ 0x60, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x60, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x61, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x61, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x62, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x62, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x63, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x63, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x64, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x64, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x65, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x65, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x66, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x66, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x67, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x67, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x68, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x68, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
 
-	{ 0x70, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x70, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x71, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x71, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x72, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x72, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x73, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x73, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x74, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x74, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x75, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x75, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x76, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x76, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x77, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x77, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x78, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x78, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
 
 	/* Errata 354 - Fam10 C2
 	 * System software should set bit 6 of
F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
-	{ 0x40, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x40, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x41, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x41, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x42, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x42, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x43, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x43, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x44, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x44, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x45, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x45, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x46, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x46, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x47, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x47, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x48, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x48, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
 
-	{ 0x50, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x50, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x51, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x51, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x52, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x52, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x53, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x53, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x54, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x54, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x55, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x55, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x56, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x56, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x57, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x57, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
-	{ 0x58, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x58, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00000040, 0x00000040 },
 
 	/* Errata 327 - Fam10 C2
@@ -400,15 +400,15 @@ 
 	 * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
 	 * Link Phy Impedance Register[RttIndex]
 	 * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
-	{ 0xC0, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0xC0, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x40040000, 0xe01F0000 },
-	{ 0xD0, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0xD0, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x40040000, 0xe01F0000 },
 
-	{ 0x520A, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x520A, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00004000, 0x00006000 },	/* HT_PHY_DLL_REG */
 
-	{ 0x530A, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+	{ 0x530A, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
HTPHY_LINKTYPE_ALL,
 	  0x00004000, 0x00006000 },	/* HT_PHY_DLL_REG */
 
 	{ 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Index: src/northbridge/amd/amdmct/wrappers/mcti_d.c
===================================================================
--- src/northbridge/amd/amdmct/wrappers/mcti_d.c	(revision 4426)
+++ src/northbridge/amd/amdmct/wrappers/mcti_d.c	(working copy)
@@ -394,7 +394,7 @@ 
 
 void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct
DCTStatStruc *pDCTstatA)
 {
-	if (pDCTstatA->LogicalCPUID & AMD_RB_C2) {
+	if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2)) {
 		vErrata350(pMCTstat, pDCTstatA);
 	}
 }
Index: src/northbridge/amd/amdmct/amddefs.h
===================================================================
--- src/northbridge/amd/amdmct/amddefs.h	(revision 4426)
+++ src/northbridge/amd/amdmct/amddefs.h	(working copy)
@@ -41,6 +41,7 @@ 
 #define	AMD_DR_BA	0x00400000	/* Barcelona BA */
 #define	AMD_DR_B3	0x00800000	/* Barcelona B3 */
 #define	AMD_RB_C2	0x01000000	/* Shanghai C2 */
+#define	AMD_DA_C2	0x02000000	/* XXXX C2 */
 
 /*
  * Groups - Create as many as you wish, from the above public values
Index: src/northbridge/amd/amdfam10/raminit_amdmct.c
===================================================================
--- src/northbridge/amd/amdfam10/raminit_amdmct.c	(revision 4426)
+++ src/northbridge/amd/amdfam10/raminit_amdmct.c	(working copy)
@@ -149,9 +149,12 @@ 
 	case 0x10023:
 		ret = AMD_DR_B3;
 		break;
-	case 0x10062:
+	case 0x10042:
 		ret = AMD_RB_C2;
 		break;
+	case 0x10062:
+		ret = AMD_DA_C2;
+		break;
 	default:
 		/* FIXME: mabe we should die() here. */
 		print_err("FIXME! CPU Version unknown or not supported!