Patchwork VIA VX900

diff -urp r1548/chipset_enable.c new/chipset_enable.c
--- r1548/chipset_enable.c	2012-07-20 09:45:51.000000000 +0200
+++ new/chipset_enable.c	2012-07-23 14:00:11.000000000 +0200
@@ -510,7 +510,13 @@  static int enable_flash_tunnelcreek(stru
 static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
 {
 	/* Do we really need no write enable? */
-	return via_init_spi(dev);
+	return via_init_spi(dev, 1);
+}
+
+static int enable_flash_vx900_spi(struct pci_dev *dev, const char *name)
+{
+	/* Do we really need no write enable? */
+	return via_init_spi(dev, 0);
 }
 
 static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
@@ -1271,6 +1277,7 @@  const struct penable chipset_enables[] =
 	{0x1106, 0x8324, OK, "VIA", "CX700",		enable_flash_vt823x},
 	{0x1106, 0x8353, OK, "VIA", "VX800/VX820",	enable_flash_vt8237s_spi},
 	{0x1106, 0x8409, OK, "VIA", "VX855/VX875",	enable_flash_vt823x},
+	{0x1106, 0x8410, OK, "VIA", "VX900",		enable_flash_vx900_spi},
 	{0x1166, 0x0200, OK, "Broadcom", "OSB4",	enable_flash_osb4},
 	{0x1166, 0x0205, OK, "Broadcom", "HT-1000",	enable_flash_ht1000},
 	{0x17f3, 0x6030, OK, "RDC", "R8610/R3210",	enable_flash_rdc_r8610},
diff -urp r1548/ichspi.c new/ichspi.c
--- r1548/ichspi.c	2012-07-20 09:45:51.000000000 +0200
+++ new/ichspi.c	2012-07-23 13:58:31.000000000 +0200
@@ -1843,14 +1843,29 @@  static const struct spi_programmer spi_p
 	.write_aai = default_spi_write_aai,
 };
 
-int via_init_spi(struct pci_dev *dev)
+int via_init_spi(struct pci_dev *dev, int spi_base_is_mmio_base)
 {
 	uint32_t mmio_base;
 	int i;
 
 	mmio_base = (pci_read_long(dev, 0xbc)) << 8;
 	msg_pdbg("MMIO base at = 0x%x\n", mmio_base);
-	ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
+	if (spi_base_is_mmio_base) {
+		ich_spibar = physmap("VT8237S SPI MMIO registers", mmio_base, 0x70);
+	} else {
+		uint32_t spi_mm_base;
+		void *mmio_base_physmapped = NULL; 
+		mmio_base_physmapped = physmap("VX900 SPI MMIO registers", mmio_base, 0x04);
+		/* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. Check it: */
+		if ((mmio_readl(mmio_base_physmapped + 0) & 0x01) == 0) {
+			msg_pdbg ("SPI Bus0 disabled!\n");
+			return 1;
+		}
+		/* Offset 1-3 has  SPI Bus Memory Map Base Address: */
+		spi_mm_base = mmio_readl(mmio_base_physmapped + 0) & 0xFFFFFF00; 
+		msg_pdbg("SPI Bus0 base at = 0x%x\n", spi_mm_base);
+		ich_spibar = physmap("VX900 SPI Bus0 MMIO registers", spi_mm_base, 0x70); 
+	}
 
 	/* Not sure if it speaks all these bus protocols. */
 	internal_buses_supported = BUS_LPC | BUS_FWH;
diff -urp r1548/programmer.h new/programmer.h
--- r1548/programmer.h	2012-07-20 09:45:51.000000000 +0200
+++ new/programmer.h	2012-07-23 14:16:49.000000000 +0200
@@ -560,7 +560,7 @@  enum ich_chipset {
 extern uint32_t ichspi_bbar;
 int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 		 enum ich_chipset ich_generation);
-int via_init_spi(struct pci_dev *dev);
+int via_init_spi(struct pci_dev *dev, int spi_base_is_mmio_base);
 
 /* it85spi.c */
 int it85xx_spi_init(struct superio s);