Patchwork Add board enable for ASUS M3N78-EM.

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Submitter Stefan Tauner
Date 2012-09-12 22:05:10
Message ID <1347487510-14671-1-git-send-email-stefan.tauner@student.tuwien.ac.at>
Download mbox | patch
Permalink /patch/3747/
State Deferred
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Comments

Stefan Tauner - 2012-09-12 22:05:10
From: Joshua Roys <roysjosh@gmail.com>

This does not work* (yet), but we want to keep it in patchwork for
further refinement.

* http://paste.flashrom.org/view.php?id=954

---
 board_enable.c   |   12 ++++++++++++
 chipset_enable.c |   15 ++++++++++++++-
 mcp6x_spi.c      |   11 +++++++++++
 3 files changed, 37 insertions(+), 1 deletion(-)

Patch

diff --git a/board_enable.c b/board_enable.c
index 2668f10..540eb7d 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -878,6 +878,17 @@  static int board_msi_kt4v(void)
 	return ret;
 }
 
+static int board_asus_m3n78em_enable(void)
+{
+	uint8_t tmp;
+
+	tmp = INB(0xA02);
+	tmp |= 0x01;
+	OUTB(tmp, 0xA02);
+
+	return 0;
+}
+
 /*
  * Suited for:
  *  - ASUS P5A
@@ -2323,6 +2334,7 @@  const struct board_match board_matches[] = {
 	{0x10de, 0x0264, 0x1043, 0x81bc,  0x10de, 0x02f0, 0x1043, 0x81cd, NULL,         NULL, NULL,           P3, "ASUS",        "A8N-VM CSM",            0,   OK, w83627ehf_gpio22_raise_2e},
 	{0x10DE, 0x0264, 0x1043, 0x81C0,  0x10DE, 0x0260, 0x1043, 0x81C0, NULL,         NULL, NULL,           P3, "ASUS",        "M2NBP-VM CSM",          0,   OK, nvidia_mcp_gpio0_raise},
 	{0x1106, 0x1336, 0x1043, 0x80ed,  0x1106, 0x3288, 0x1043, 0x8249, NULL,         NULL, NULL,           P3, "ASUS",        "M2V-MX",                0,   OK, via_vt823x_gpio5_raise},
+	{0x10de, 0x075c, 0x1043, 0x82f2,  0x10de, 0x0752, 0x1043, 0x82f2, NULL,         NULL, NULL,           P3, "ASUS",        "M3N78-EM",              0,   OK, board_asus_m3n78em_enable},
 	{0x8086, 0x24cc,      0,      0,  0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$",     NULL, NULL,           P3, "ASUS",        "M6Ne",                  0,   NT, intel_ich_gpio43_raise},
 	{0x8086, 0x7180,      0,      0,  0x8086, 0x7110,      0,      0, "^OPLX-M$",   NULL, NULL,           P3, "ASUS",        "OPLX-M",                0,   NT, intel_piix4_gpo18_lower},
 	{0x8086, 0x7190,      0,      0,  0x8086, 0x7110,      0,      0, "^P2B-N$",    NULL, NULL,           P3, "ASUS",        "P2B-N",                 0,   OK, intel_piix4_gpo18_lower},
diff --git a/chipset_enable.c b/chipset_enable.c
index e1684f9..07b7671 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1157,6 +1157,8 @@  static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
 
 	msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
 
+	ret = enable_flash_mcp55(dev, name);
+
 	/* dev is the ISA bridge. No idea what the stuff below does. */
 	val = pci_read_byte(dev, 0x8a);
 	msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
@@ -1164,7 +1166,6 @@  static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
 
 	switch ((val >> 5) & 0x3) {
 	case 0x0:
-		ret = enable_flash_mcp55(dev, name);
 		internal_buses_supported = BUS_LPC;
 		msg_pdbg("Flash bus type is LPC\n");
 		break;
@@ -1198,6 +1199,18 @@  static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
 	if (mcp6x_spi_init(want_spi))
 		ret = 1;
 
+	rpci_write_byte(dev, 0x8e, 0x00);
+	if (pci_read_byte(dev, 0x8e) != 0x00) {
+		msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
+			  "(WARNING ONLY).\n", 0x8e, 0x00, name);
+	}
+
+	rpci_write_byte(dev, 0x8f, 0x00);
+	if (pci_read_byte(dev, 0x8f) != 0x00) {
+		msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
+			  "(WARNING ONLY).\n", 0x8f, 0x00, name);
+	}
+
 out_msg:
 	msg_pinfo("Please send the output of \"flashrom -V\" to "
 		  "flashrom@flashrom.org with\n"
diff --git a/mcp6x_spi.c b/mcp6x_spi.c
index ac40557..abe8e0d 100644
--- a/mcp6x_spi.c
+++ b/mcp6x_spi.c
@@ -104,6 +104,7 @@  static const struct bitbang_spi_master bitbang_spi_master_mcp6x = {
 
 int mcp6x_spi_init(int want_spi)
 {
+	uint8_t old, new;
 	uint16_t status;
 	uint32_t mcp6x_spibaraddr;
 	struct pci_dev *smbusdev;
@@ -125,6 +126,16 @@  int mcp6x_spi_init(int want_spi)
 		smbusdev->bus, smbusdev->dev, smbusdev->func);
 
 
+	old = pci_read_byte(smbusdev, 0xe7);
+	new = old | 0x80;
+	if (new != old) {
+		rpci_write_byte(smbusdev, 0xe7, new);
+		if (pci_read_byte(smbusdev, 0xe7) != new) {
+			msg_pinfo("Setting register 0x%x to 0x%x failed "
+				  "(WARNING ONLY).\n", 0xe7, new);
+		}
+	}
+
 	/* Locate the BAR where the SPI interface lives. */
 	mcp6x_spibaraddr = pci_read_long(smbusdev, 0x74);
 	/* BAR size is 64k, bits 15..4 are zero, bit 3..0 declare a