From patchwork Sat Oct 10 15:10:39 2009
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Subject: serialice: Add MSI MS-6178 support, and HAVE_SSE
Date: Sat, 10 Oct 2009 15:10:39 -0000
From: Uwe Hermann <uwe@hermann-uwe.de>
X-Patchwork-Id: 384
Message-Id: <20091010151039.GC15511@greenwood>
To: coreboot@coreboot.org

See patch.


Uwe.


Add MSI MS-6178 support for SerialICE (i810, ICH0).

Also add a HAVE_SSE config option, otherwise SerialICE won't work on
older CPUs (as in the MS-6178) without SSE.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>

Index: config.h
===================================================================
--- config.h	(Revision 10)
+++ config.h	(Arbeitskopie)
@@ -20,5 +20,7 @@
 #define ECHO_MODE	1
 #define SIO_SPEED	115200
 #define SIO_PORT	0x3f8
+#define HAVE_SSE	1	/* Set to 0 for CPUs without SSE. */
 //#define MAINBOARD	"kontron_986lcd-m.c"
 //#define MAINBOARD	"intel_d945gclf.c"
+//#define MAINBOARD	"msi_ms6178.c"
Index: mainboard/msi_ms6178.c
===================================================================
--- mainboard/msi_ms6178.c	(Revision 0)
+++ mainboard/msi_ms6178.c	(Revision 0)
@@ -0,0 +1,72 @@
+/*
+ * SerialICE 
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define PMBASE			0x40
+#define COM_DEC			0xe0
+#define LPC_EN			0xe6
+
+#define PMBASE_ADDR		0x500
+#define TCOBASE			(PMBASE + 0x60)
+#define TCO1_STS		(TCOBASE + 0x04)
+#define TCO2_STS		(TCOBASE + 0x06)
+#define TCO1_CNT		(TCOBASE + 0x08)
+
+#define SUPERIO_CONFIG_PORT	0x2e
+
+static void southbridge_init(void)
+{
+	u16 reg16;
+
+	/* Disable watchdog. */
+	pci_write_config32(PCI_ADDR(0, 0x1f, 0, PMBASE), PMBASE_ADDR | 1);
+	reg16 = inw(TCO1_CNT);
+	reg16 |= (1 << 11);		/* Halt TCO timer. */
+	outw(reg16, TCO1_CNT);
+	outw(0x0008, TCO1_STS);		/* Clear timeout status. */
+	outw(0x0002, TCO2_STS);		/* Clear second timeout status. */
+
+	/* Set COM1/COM2 decode range. */
+	pci_write_config8(PCI_ADDR(0, 0x1f, 0, COM_DEC), 0x10);
+
+	/* Enable COM1, COM2, and Super I/O config registers 0x2e/0x4e. */
+	pci_write_config16(PCI_ADDR(0, 0x1f, 0, LPC_EN), 0x3003);
+}
+
+static void superio_init(void)
+{
+	pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT);
+
+	/* Set CLKSEL=1 to select 48 MHz (otherwise serial won't work). */
+	pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc4);
+
+	pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */
+	pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
+	pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8);
+	pnp_set_irq0(SUPERIO_CONFIG_PORT, 4);
+	pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
+
+	pnp_exit_ext_func_mode(0x2e);
+}
+
+static void chipset_init(void)
+{
+	southbridge_init();
+	superio_init();
+}
Index: start.S
===================================================================
--- start.S	(Revision 10)
+++ start.S	(Arbeitskopie)
@@ -17,6 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include "config.h"
+
 	.code32
 
 _c_main:
@@ -28,9 +30,11 @@
 	movl	%ebp, %eax
 
 	/* enable SSE */
+#if HAVE_SSE
 	movl %cr4, %eax
 	orl $(3<<9), %eax
 	movl %eax, %cr4
+#endif
 
 	xorl	%esp,%esp
 	movl	$0x7f,%esp #Start address of XMM/MMX stack.