From patchwork Tue Oct 13 16:27:00 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: Technexion Tim-5690 mainboard Date: Tue, 13 Oct 2009 16:27:00 -0000 From: Myles Watson X-Patchwork-Id: 398 Message-Id: <2831fecf0910130927m41c531e7w4ede51051d3e1dcc@mail.gmail.com> To: Libra Li Cc: coreboot On Tue, Oct 13, 2009 at 4:34 AM, Libra Li wrote: > Hi, > >     This patch support for the Technexion Tim-5690 mainboard. >     It's an embedded AMD RS690/SB600 mainboard. > >     http://www.technexion.com/index.php/tim-5690 > >     Signed-off-by: Libra Li This is the same patch starting with the tim8690 and adding Kconfig support. There are very few differences between the two boards. I'm adding my Signed-off-by for the Kconfig part. Build-tested. Signed-off-by: Myles Watson Thanks, Myles Acked-by: Stefan Reinauer Index: svn/src/mainboard/technexion/tim5690/Config.lb =================================================================== --- svn.orig/src/mainboard/technexion/tim5690/Config.lb +++ svn/src/mainboard/technexion/tim5690/Config.lb @@ -139,7 +139,7 @@ config chip.h #Define vga_rom_address = 0xfff80000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. #Define gfx_dual_slot, 0: single slot, 1: dual slot #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable #Define gfx_tmds, 0: didn't support TMDS, 1: support @@ -160,7 +160,10 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff80000" + register "rom_address" = "0xfff80000" #512KB + #register "rom_address" = "0xfff00000" #1024KB + #register "rom_address" = "0xffe00000" #2048KB + #register "rom_address" = "0xffc00000" #4096KB end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -171,14 +174,17 @@ chip northbridge/amd/amdk8/root_complex device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge register "vga_rom_address" = "0xfff80000" + #register "vga_rom_address" = "0xfff00000" + #register "vga_rom_address" = "0xffe00000" + #register "vga_rom_address" = "0xffc00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "0" register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" + register "gfx_tmds" = "1" register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" + register "gfx_reconfiguration" = "0" register "gfx_link_width" = "0" end chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus @@ -216,11 +222,11 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 on # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 on # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end Index: svn/src/mainboard/technexion/tim5690/Options.lb =================================================================== --- svn.orig/src/mainboard/technexion/tim5690/Options.lb +++ svn/src/mainboard/technexion/tim5690/Options.lb @@ -90,6 +90,7 @@ uses CONFIG_USE_PRINTK_IN_CAR uses CONFIG_VIDEO_MB uses CONFIG_GFXUMA uses CONFIG_HAVE_MAINBOARD_RESOURCES +uses CONFIG_VGA_ROM_RUN ### ### Build options @@ -152,13 +153,13 @@ default CONFIG_MAX_CPUS=2 default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1 - #1G memory hole default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 +default CONFIG_VGA_ROM_RUN=1 # BTDC: Only one HT device on Herring. #HT Unit ID offset @@ -189,7 +190,7 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default CONFIG_MAINBOARD_PART_NUMBER="tim8690" +default CONFIG_MAINBOARD_PART_NUMBER="tim5690" default CONFIG_MAINBOARD_VENDOR="technexion" default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 Index: svn/src/mainboard/technexion/tim5690/acpi/dsdt.asl =================================================================== --- svn.orig/src/mainboard/technexion/tim5690/acpi/dsdt.asl +++ svn/src/mainboard/technexion/tim5690/acpi/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "TECHNEXION", /* OEMID */ - "TIM-8690", /* TABLE ID */ + "TIM-5690", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -934,10 +934,10 @@ DefinitionBlock ( */ /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } + //Method(_L03) { + // /* DBGO("\\_GPE\\_L00\n") */ + // Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + //} /* General event 4 */ /* Method(_L04) { @@ -1610,7 +1610,7 @@ DefinitionBlock ( Device(PWRB) { /* Start Power button device */ Name(_HID, EISAID("PNP0C0C")) Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + //Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ Name(_STA, 0x0B) /* sata is invisible */ } } /* End \_SB scope */ Index: svn/src/mainboard/technexion/tim5690/acpi/usb.asl =================================================================== --- svn.orig/src/mainboard/technexion/tim5690/acpi/usb.asl +++ svn/src/mainboard/technexion/tim5690/acpi/usb.asl @@ -97,17 +97,18 @@ If (LLessEqual(UOM4,9)) { } /* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} +/* If (LLessEqual(UOM5,9)) { +* Scope (\_GPE) { +* Method (_L1A) { +* UCOC() +* if (LEqual(GPB5,PLC5)) { +* Not(PLC5,PLC5) +* Store(PLC5, \_SB.PT5D) +* } +* } +* } +* } +*/ /* USB Port 6 overcurrent uses Gpm 6 */ If (LLessEqual(UOM6,9)) { Index: svn/src/mainboard/technexion/tim5690/cache_as_ram_auto.c =================================================================== --- svn.orig/src/mainboard/technexion/tim5690/cache_as_ram_auto.c +++ svn/src/mainboard/technexion/tim5690/cache_as_ram_auto.c @@ -179,7 +179,7 @@ void real_main(unsigned long bist, unsig report_bist_failure(bist); printk_debug("bsp_apicid=0x%x\n", bsp_apicid); - setup_tim8690_resource_map(); + setup_tim5690_resource_map(); setup_coherent_ht_domain(); Index: svn/src/mainboard/technexion/tim5690/mainboard.c =================================================================== --- svn.orig/src/mainboard/technexion/tim5690/mainboard.c +++ svn/src/mainboard/technexion/tim5690/mainboard.c @@ -49,7 +49,7 @@ uint64_t uma_memory_base, uma_memory_siz /*************************************************** -* This board, the TIM-8690 has two Marvel 88e5056 PCI-E +* This board, the TIM-5690 has two Marvel 88e5056 PCI-E * 10/100/1000 chips on board. * Both of their pin PERSTn pins are connected to GPIO 5 of the * SB600 southbridge. @@ -57,28 +57,25 @@ uint64_t uma_memory_base, uma_memory_siz static void enable_onboard_nic() { - u8 byte; - device_t sm_dev; - - - printk_info("enable_onboard_nic.\n"); - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0x9a); - byte |= ( 1 << 7); - pci_write_config8(sm_dev, 0x9a, byte); + u8 byte; + device_t sm_dev; + printk_info("enable_onboard_nic.\n"); - byte=pm_ioread(0x59); - byte &= ~( 1<< 5); - pm_iowrite(0x59,byte); + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + byte = pci_read_config8(sm_dev, 0x9a); + byte |= ( 1 << 7); + pci_write_config8(sm_dev, 0x9a, byte); + + byte=pm_ioread(0x59); + byte &= ~( 1<< 5); + pm_iowrite(0x59,byte); - byte = pci_read_config8(sm_dev, 0xA8); + byte = pci_read_config8(sm_dev, 0xA8); - byte |= (1 << 1); //set bit 1 to high - pci_write_config8(sm_dev, 0xA8, byte); + byte |= (1 << 1); //set bit 1 to high + pci_write_config8(sm_dev, 0xA8, byte); } /* set thermal config @@ -88,6 +85,7 @@ static void set_thermal_config() u8 byte; u16 word; device_t sm_dev; + struct bus pbus; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -145,15 +143,15 @@ static void set_thermal_config() } /************************************************* -* enable the dedicated function in tim8690 board. +* enable the dedicated function in tim5690 board. * This function called early than rs690_enable. *************************************************/ -void tim8690_enable(device_t dev) +void tim5690_enable(device_t dev) { struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; - printk_info("Mainboard tim8690 Enable. dev=0x%p\n", dev); + printk_info("Mainboard tim5690 Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; @@ -214,6 +212,6 @@ int add_mainboard_resources(struct lb_me } struct chip_operations mainboard_ops = { - CHIP_NAME("TechNexion TIM-8690 Mainboard") - .enable_dev = tim8690_enable, + CHIP_NAME("TechNexion TIM-5690 Mainboard") + .enable_dev = tim5690_enable, }; Index: svn/src/mainboard/technexion/tim5690/mptable.c =================================================================== --- svn.orig/src/mainboard/technexion/tim5690/mptable.c +++ svn/src/mainboard/technexion/tim5690/mptable.c @@ -42,7 +42,7 @@ void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "ATI "; - static const char productid[12] = "TIM8690 "; + static const char productid[12] = "TIM5690 "; struct mp_config_table *mc; int j; Index: svn/src/mainboard/technexion/tim5690/resourcemap.c =================================================================== --- svn.orig/src/mainboard/technexion/tim5690/resourcemap.c +++ svn/src/mainboard/technexion/tim5690/resourcemap.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static void setup_tim8690_resource_map(void) +static void setup_tim5690_resource_map(void) { static const unsigned int register_values[] = { /* Careful set limit registers before base registers which contain the enables */ Index: svn/src/southbridge/amd/sb600/sb600_early_setup.c =================================================================== --- svn.orig/src/southbridge/amd/sb600/sb600_early_setup.c +++ svn/src/southbridge/amd/sb600/sb600_early_setup.c @@ -106,8 +106,8 @@ static void sb600_lpc_init(void) pci_write_config16(dev, 0x68, 0x000e); /* enable LPC ROM range mirroring end 0x000f(ffff) */ pci_write_config16(dev, 0x6a, 0x000f); - /* enable LPC ROM range start, 0xfff8(0000): 512KB, 0xfff0(0000): 1MB */ - pci_write_config16(dev, 0x6c, 0xfff0); + /* enable LPC ROM range start, 0xfff8(0000): 512KB, 0xfff0(0000): 1MB, 0xffe0(0000): 2MB, 0xffc0(0000): 4MB */ + pci_write_config16(dev, 0x6c, 0xffc0); /* enable LPC ROM range end at 0xffff(ffff) */ pci_write_config16(dev, 0x6e, 0xffff); } Index: svn/src/mainboard/technexion/tim5690/Kconfig =================================================================== --- svn.orig/src/mainboard/technexion/tim5690/Kconfig +++ svn/src/mainboard/technexion/tim5690/Kconfig @@ -1,5 +1,5 @@ -config BOARD_TECHNEXION_TIM8690 - bool "Tim8690" +config BOARD_TECHNEXION_TIM5690 + bool "Tim5690" select ARCH_X86 select CPU_AMD_K8 select CPU_AMD_SOCKET_S1G1 @@ -21,85 +21,85 @@ config BOARD_TECHNEXION_TIM8690 config MAINBOARD_DIR string - default technexion/tim8690 - depends on BOARD_TECHNEXION_TIM8690 + default technexion/tim5690 + depends on BOARD_TECHNEXION_TIM5690 config DCACHE_RAM_BASE hex default 0xc8000 - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 config DCACHE_RAM_SIZE hex default 0x08000 - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 config DCACHE_RAM_GLOBAL_VAR_SIZE hex default 0x01000 - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 config APIC_ID_OFFSET hex default 0x8 - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 config LB_CKS_RANGE_END int default 122 - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 config LB_CKS_LOC int default 123 - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 config MAINBOARD_PART_NUMBER string - default "tim8690" - depends on BOARD_TECHNEXION_TIM8690 + default "tim5690" + depends on BOARD_TECHNEXION_TIM5690 config HW_MEM_HOLE_SIZEK hex default 0x100000 - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 config MAX_CPUS int default 2 - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 config MAX_PHYSICAL_CPUS int default 1 - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 config HW_MEM_HOLE_SIZE_AUTO_INC bool default n - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 config SB_HT_CHAIN_ON_BUS0 int default 2 - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 config HT_CHAIN_END_UNITID_BASE hex default 0x6 - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 config HT_CHAIN_UNITID_BASE hex default 0xa - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 config USE_INIT bool default n - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 config IRQ_SLOT_COUNT int default 11 - depends on BOARD_TECHNEXION_TIM8690 + depends on BOARD_TECHNEXION_TIM5690 Index: svn/src/mainboard/technexion/tim5690/devicetree.cb =================================================================== --- svn.orig/src/mainboard/technexion/tim5690/devicetree.cb +++ svn/src/mainboard/technexion/tim5690/devicetree.cb @@ -23,7 +23,10 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff80000" + register "rom_address" = "0xfff80000" #512KB + #register "rom_address" = "0xfff00000" #1024KB + #register "rom_address" = "0xffe00000" #2048KB + #register "rom_address" = "0xffc00000" #4096KB end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -34,14 +37,17 @@ chip northbridge/amd/amdk8/root_complex device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge register "vga_rom_address" = "0xfff80000" + #register "vga_rom_address" = "0xfff00000" + #register "vga_rom_address" = "0xffe00000" + #register "vga_rom_address" = "0xffc00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "0" register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" + register "gfx_tmds" = "1" register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" + register "gfx_reconfiguration" = "0" register "gfx_link_width" = "0" end chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus @@ -79,11 +85,11 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 on # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 on # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end Index: svn/src/mainboard/technexion/Kconfig =================================================================== --- svn.orig/src/mainboard/technexion/Kconfig +++ svn/src/mainboard/technexion/Kconfig @@ -3,6 +3,7 @@ choice depends on VENDOR_TECHNEXION source "src/mainboard/technexion/tim8690/Kconfig" +source "src/mainboard/technexion/tim5690/Kconfig" endchoice Index: svn/src/mainboard/technexion/org5690/devicetree.cb =================================================================== --- svn.orig/src/mainboard/technexion/org5690/devicetree.cb +++ /dev/null @@ -1,128 +0,0 @@ -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff80000 -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_S1G1 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff80000" - end - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff80000" - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex -